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  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsUsb.h 69 #define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale
92 #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
PchRegsSpi.h 47 #define B_PCH_SPI_HSFS_FDV BIT14 // Flash Descriptor Valid
76 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
97 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select
PchRegsSata.h 81 #define B_PCH_SATA_PCISTS_SSE BIT14 // Signaled System Error
170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
171 #define B_PCH_SATA_PORT6_DISABLED BIT14
187 #define B_PCH_SATA_PCS_PORT6_DET BIT14 // Port 6 Present
PchRegsPcu.h 89 #define B_PCH_LPC_DEV_STS_SSE BIT14 // Signaled System Error
196 #define B_PCH_LPC_FWH_BIOS_DEC_EF0 BIT14 // F0-F8 Enable
353 #define B_PCH_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) // INTD Mask
358 #define V_PCH_ILB_DXXIR_IDR_PIRQE BIT14 // INTD Mapping to IRQ E
359 #define V_PCH_ILB_DXXIR_IDR_PIRQF (BIT14 | BIT12) // INTD Mapping to IRQ F
360 #define V_PCH_ILB_DXXIR_IDR_PIRQG (BIT14 | BIT13) // INTD Mapping to IRQ G
361 #define V_PCH_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) // INTD Mapping to IRQ H
465 #define B_PCH_ACPI_PM1_STS_WAK_PCIE0 BIT14 // PCI Express 0 Wake Status
484 #define B_PCH_ACPI_PM1_WAK_DIS_PCIE0 BIT14 // PCI Express 0 Disable
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h 102 #define EPHSR_LINK_OK BIT14
111 #define RCR_FILT_CAR BIT14
144 #define CTR_RCV_BAD BIT14
179 #define PTR_AUTO_INCR BIT14
196 #define MGMT_MSK_CRS100 BIT14
209 #define RX_BROADCAST BIT14
251 #define PHYCR_LOOPBK BIT14 // Set loopback mode
264 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h 31 #undef BIT14
67 #define BIT14 0x00004000U
  /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h 99 #define IRQCFG_INT_DEAS_CLR BIT14 // Clear the deassertion counter
112 #define INSTS_RXE BIT14 // Receiver Error
154 #define PHYCR_LOOPBK BIT14 // Set loopback mode
167 #define PHYSTS_100BASETX_FDPLX BIT14 // 100Mbps Full-Duplex ability
237 #define TXCFG_TXD_DUMP BIT14 // Clear Tx Data FIFO
  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Dma.h 101 #define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)
103 #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
Omap3530Prcm.h 115 #define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
140 #define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Dma.h 101 #define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)
103 #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
Omap3530Prcm.h 115 #define CM_FCLKEN_PER_EN_GPIO3_ENABLE BIT14
140 #define CM_ICLKEN_PER_EN_GPIO3_ENABLE BIT14
  /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h 71 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
VirtioNet.h 55 #define VIRTIO_NET_F_HOST_UFO BIT14 // host can receive UFO
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
QuarkNcSocId.h 297 #define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14
446 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)
448 #define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14)
457 #define B_QNC_PM1BLK_PM1E_PWAKED (BIT14)
481 #define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO
488 #define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO
659 #define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask
    [all...]
  /device/linaro/bootloader/edk2/MdePkg/Library/BasePrintLib/
PrintLibInternal.h 37 #define UNSIGNED_TYPE BIT14
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
CommonIncludes.h 102 #define BIT14 0x00004000
  /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/
IdeData.h 269 #define SITRE BIT14
  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
PchRegs.h 60 #define BIT14 0x4000
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/
UartInit.c 31 #define B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR BIT14 // SUS Well Power Failure
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
BoardFeatures.h 61 #define B_BOARD_FEATURES_VIIV BIT14
155 #define B_BOARD_FEATURES_TPM BIT14
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h 97 #define MCI_STATUS_CMD_TXFIFOHALFEMPTY BIT14
  /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
BaseTypes.h 235 #define BIT14 0x00004000
  /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaBusDxe/
AtaPassThruExecute.c 356 if ((PhyLogicSectorSupport & (BIT14 | BIT15)) == BIT14) {
365 if ((IdentifyData->alignment_logic_in_phy_blocks & (BIT14 | BIT15)) == BIT14) {
    [all...]
  /system/bt/embdrv/sbc/decoder/include/
oi_stddefs.h 265 #define BIT14 \
  /bionic/libc/kernel/uapi/linux/
synclink.h 37 #define BIT14 0x4000

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