HomeSort by relevance Sort by last modified time
    Searched refs:BIT15 (Results 1 - 25 of 99) sorted by null

1 2 3 4

  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsHda.h 50 #define B_PCH_HDA_PCS_PMES BIT15 // PME Status
PchRegsUsb.h 68 #define B_PCH_EHCI_PWR_CNTL_STS_PME_STS BIT15 // PME Status
91 #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS BIT15
PchRegsSpi.h 46 #define B_PCH_SPI_HSFS_FLOCKDN BIT15 // Flash Configuration Lock-Down
62 #define B_PCH_SPI_PR0_RPE BIT15 // Read Protection Enable
68 #define B_PCH_SPI_PR1_RPE BIT15 // Read Protection Enable
76 #define B_PCH_SPI_OPTYPE7_MASK (BIT15 | BIT14) // Opcode Type 7 Mask
PchRegsSata.h 80 #define B_PCH_SATA_PCISTS_DPE BIT15 // Detected Parity Error
160 #define B_PCH_SATA_PMCS_PMES BIT15 // PME Status
186 #define B_PCH_SATA_PCS_OOB_RETRY BIT15 // OOB Retry Mode
PchRegsLpss.h 119 #define B_PCH_LPSS_DMAC_PCS_PMESTS BIT15 // PME Status
204 #define B_PCH_LPSS_I2C_PCS_PMESTS BIT15 // PME Status
291 #define B_PCH_LPSS_PWM_PCS_PMESTS BIT15 // PME Status
378 #define B_PCH_LPSS_HSUART_PCS_PMESTS BIT15 // PME Status
470 #define B_PCH_LPSS_SPI_PCS_PMESTS BIT15 // PME Status
PchRegsPcu.h 88 #define B_PCH_LPC_DEV_STS_DPE BIT15 // Detected Parity Error
195 #define B_PCH_LPC_FWH_BIOS_DEC_EF8 BIT15 // F8-FF Enable
464 #define B_PCH_ACPI_PM1_STS_WAK BIT15 // Wake Status
    [all...]
  /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Prcm.h 43 #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
45 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
47 #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
49 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
118 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
143 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
Omap3530Dma.h 102 #define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)
103 #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
Omap3530I2c.h 47 #define I2C_EN BIT15
  /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Prcm.h 43 #define CM_FCLKEN1_CORE_EN_I2C1_MASK BIT15
45 #define CM_FCLKEN1_CORE_EN_I2C1_ENABLE BIT15
47 #define CM_ICLKEN1_CORE_EN_I2C1_MASK BIT15
49 #define CM_ICLKEN1_CORE_EN_I2C1_ENABLE BIT15
118 #define CM_FCLKEN_PER_EN_GPIO4_ENABLE BIT15
143 #define CM_ICLKEN_PER_EN_GPIO4_ENABLE BIT15
Omap3530Dma.h 102 #define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)
103 #define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
Omap3530I2c.h 47 #define I2C_EN BIT15
  /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
SP804Timer.h 48 #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK
  /device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/
PciPowerManagement.c 82 PowerManagementCSR |= BIT15;
  /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/
PciPowerManagement.c 69 PowerManagementCSR |= BIT15;
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h 84 #define TCR_SWFDUP BIT15
112 #define RCR_SOFT_RST BIT15
132 #define CR_EPH_POWER_EN BIT15
173 #define FIFO_REMPTY BIT15
180 #define PTR_RCV BIT15
210 #define RX_ALGN_ERR BIT15
252 #define PHYCR_RESET BIT15 // Do a PHY reset
265 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
  /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h 73 #define RXSTATUS_ES BIT15 // Reports any error from bits 1,6,7 and 11
86 #define TXSTATUS_ES BIT15 // Reports any errors from bits 1,2,8,9,10 and 11
113 #define INSTS_RWT BIT15 // Packet > 2048 bytes received
155 #define PHYCR_RESET BIT15 // Do a PHY reset
168 #define PHYSTS_100BASE_T4 BIT15 // Base T4 ability
209 #define MACCR_HO BIT15 // Hash Only Filtering Mode
228 #define RXCFG_RX_DUMP BIT15 // Clear Rx data and status FIFOs
238 #define TXCFG_TXS_DUMP BIT15 // Clear Tx Status FIFO
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h 32 #undef BIT15
68 #define BIT15 0x00008000U
  /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h 71 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
VirtioNet.h 56 #define VIRTIO_NET_F_MRG_RXBUF BIT15 // guest can merge receive buffers
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
BoardFeatures.h 62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
63 #define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
157 #define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
CommonIncludes.h 101 #define BIT15 0x00008000
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
QuarkNcSocId.h 157 #define TS_ENABLE (BIT15)
446 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)
447 #define B_QNC_PM1BLK_PM1S_WAKE (BIT15)
658 #define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask
    [all...]
  /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
PchRegs.h 61 #define BIT15 0x8000
  /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/VlvPlatformInitDxe/
IgdOpRegion.h 98 #define WORD_FIELD_VALID_BIT BIT15

Completed in 198 milliseconds

1 2 3 4