| /device/linaro/bootloader/edk2/MdePkg/Library/BaseCpuLib/Ipf/ |
| CpuSleep.c | 57 AsmWriteTpr (BIT16 | Tpr);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| SP804Timer.h | 49 #define SP810_SYS_CTRL_TIMER0_EN BIT16
|
| /device/linaro/bootloader/edk2/SecurityPkg/Include/Library/ |
| Tcg2PhysicalPresenceLib.h | 44 #define TCG2_BIOS_STORAGE_MANAGEMENT_FLAG_PP_REQUIRED_FOR_ENABLE_BLOCK_SID BIT16
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 33 #undef BIT16
69 #define BIT16 0x00010000U
|
| meminit.c | 229 isbM32m(MCU, DRMC, BIT16, BIT16);
558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
566 isbM32m(DDRPHY, (B0ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
567 isbM32m(DDRPHY, (B1ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
573 isbM32m(DDRPHY, (B0OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
574 isbM32m(DDRPHY, (B1OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
585 isbM32m(DDRPHY, (DQCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (BIT16), (BIT16)); // 0 means driving DQ during DQS-preamble
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530Prcm.h | 121 #define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
146 #define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
|
| Omap3530MMCHS.h | 65 #define RSP_TYPE_136BITS BIT16
117 #define CTO BIT16
127 #define CTO_EN BIT16
142 #define CTO_SIGEN BIT16
|
| Omap3530Dma.h | 105 #define DMA4_CCR_CONST_FILL_ENABLE BIT16
|
| Omap3530Gpmc.h | 59 #define WEONTIME BIT16
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530Prcm.h | 121 #define CM_FCLKEN_PER_EN_GPIO5_ENABLE BIT16
146 #define CM_ICLKEN_PER_EN_GPIO5_ENABLE BIT16
|
| Omap3530MMCHS.h | 65 #define RSP_TYPE_136BITS BIT16
117 #define CTO BIT16
127 #define CTO_EN BIT16
142 #define CTO_SIGEN BIT16
|
| Omap3530Dma.h | 105 #define DMA4_CCR_CONST_FILL_ENABLE BIT16
|
| Omap3530Gpmc.h | 59 #define WEONTIME BIT16
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioNet.h | 57 #define VIRTIO_NET_F_STATUS BIT16 // link status available to guest
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/ |
| HwWatchdogTimer.h | 39 #define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48.
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
64 #define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
158 #define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Protocol/ |
| HwWatchdogTimer.h | 48 #define ICH_INSTAFLUSH_GPIO BIT16 // BIT 16 in GPIO Level 2 is GPIO 48.
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 100 #define BIT16 0x00010000
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 114 #define INSTS_TXSO BIT16 // Tx Status FIFO Overflow
210 #define MACCR_PASSBAD BIT16 // Receive all frames that passed filter bit
256 #define GPIO_GPIO0_PUSH_PULL BIT16
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| XhciReg.h | 78 #define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore
173 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
188 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 62 #define BIT16 0x00010000
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/ |
| UartInit.c | 32 #define B_PCH_PMC_GEN_PMCON_PWROK_FLR BIT16 // PWROK Failure
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhciReg.h | 88 #define XHC_PORTSC_LWS BIT16 // Port Link State Write Strobe
103 #define XHC_HUB_PORTSC_CSC BIT16 // Hub's Connect Status Change
|
| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/ |
| DebugCommunicationLibUsb.c | 301 while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0) {
311 MmioOr32((UINTN)&DebugPortRegister->ControlStatus, BIT16);
402 while ((MmioRead32((UINTN)&DebugPortRegister->ControlStatus) & BIT16) == 0) {
412 MmioOr32((UINTN)&DebugPortRegister->ControlStatus, BIT16);
981 while ((MmioRead32((UINTN)&UsbDebugPortRegister->ControlStatus) & (UINT32)BIT16) == 0) {
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 142 #define BYPASS_MODE (BIT15 | BIT16)
|
