/external/webrtc/webrtc/modules/audio_coding/codecs/ilbc/test/ |
iLBCtestscript.txt | 13 $EXEP/iLBCtest 20 $INP/F00.INP $OUTP/F00.BIT20 $OUTP/F00.OUT20 $INP/clean.chn 14 $EXEP/iLBCtest 20 $INP/F01.INP $OUTP/F01.BIT20 $OUTP/F01.OUT20 $INP/clean.chn 15 $EXEP/iLBCtest 20 $INP/F02.INP $OUTP/F02.BIT20 $OUTP/F02.OUT20 $INP/clean.chn 16 $EXEP/iLBCtest 20 $INP/F03.INP $OUTP/F03.BIT20 $OUTP/F03.OUT20 $INP/clean.chn 17 $EXEP/iLBCtest 20 $INP/F04.INP $OUTP/F04.BIT20 $OUTP/F04.OUT20 $INP/clean.chn 18 $EXEP/iLBCtest 20 $INP/F05.INP $OUTP/F05.BIT20 $OUTP/F05.OUT20 $INP/clean.chn 19 $EXEP/iLBCtest 20 $INP/F06.INP $OUTP/F06.BIT20 $OUTP/F06.OUT20 $INP/clean.chn 29 $EXEP/iLBCtest 20 $INP/F00.INP $OUTP/F00.BIT20 $OUTP/F00_tlm10.OUT20 $INP/tlm10.chn 30 $EXEP/iLBCtest 20 $INP/F01.INP $OUTP/F01.BIT20 $OUTP/F01_tlm10.OUT20 $INP/tlm10.chn 31 $EXEP/iLBCtest 20 $INP/F02.INP $OUTP/F02.BIT20 $OUTP/F02_tlm10.OUT20 $INP/tlm10.ch [all...] |
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
SP804Timer.h | 53 #define SP810_SYS_CTRL_TIMER2_EN BIT20
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/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
general_definitions.h | 37 #undef BIT20
73 #define BIT20 0x00100000U
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meminit.c | 520 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT20, BIT20); // SPID_INIT_COMPLETE=0
558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
566 isbM32m(DDRPHY, (B0ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
567 isbM32m(DDRPHY, (B1ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
573 isbM32m(DDRPHY, (B0OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
574 isbM32m(DDRPHY, (B1OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|B (…) [all...] |
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
Omap3530MMCHS.h | 68 #define CICE_ENABLE BIT20
118 #define DTO BIT20
131 #define DTO_EN BIT20
146 #define DTO_SIGEN BIT20
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Omap3530Dma.h | 69 #define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
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/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
Omap3530MMCHS.h | 68 #define CICE_ENABLE BIT20
118 #define DTO BIT20
131 #define DTO_EN BIT20
146 #define DTO_SIGEN BIT20
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Omap3530Dma.h | 69 #define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
PchRegsLpss.h | 63 #define B_PCH_LPSS_DMAC_STSCMD_CAPLIST BIT20 // Capability List
148 #define B_PCH_LPSS_I2C_STSCMD_CAPLIST BIT20 // Capability List
235 #define B_PCH_LPSS_PWM_STSCMD_CAPLIST BIT20 // Capability List
322 #define B_PCH_LPSS_HSUART_STSCMD_CAPLIST BIT20 // Capability List
414 #define B_PCH_LPSS_SPI_STSCMD_CAPLIST BIT20 // Capability List
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PchRegsPcu.h | [all...] |
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
CommonIncludes.h | 96 #define BIT20 0x00100000
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/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
Lan9118DxeHw.h | 118 #define INSTS_RXD_INT BIT20 // Indicates that amount of data written to RX_CFG was cleared
133 #define HWCFG_MBO BIT20 // Must Be One bit
214 #define MACCR_FDPX BIT20 // Full Duplex Mode bit
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
BoardFeatures.h | 68 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR1 BIT20
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
162 #define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT20
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
ThumbDisassembler.c | 717 Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
718 Target = SignExtend32 (Target, BIT20);
[all...] |
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/ |
OmapDmaLib.c | 93 RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
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/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
PeImage.h | 313 #define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000
315 #define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
317 #define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000
319 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
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/device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/ |
OmapDmaLib.c | 93 RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
PchRegs.h | 66 #define BIT20 0x00100000
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/external/syslinux/gpxe/src/include/gpxe/efi/IndustryStandard/ |
PeImage.h | 383 #define EFI_IMAGE_SCN_ALIGN_1BYTES BIT20 ///< 0x00100000 385 #define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000 387 #define EFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) ///< 0x00500000 389 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
AhciMode.h | 132 #define EFI_AHCI_PORT_CMD_CPD BIT20
173 #define EFI_AHCI_PORT_SERR_DE BIT20
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
XhciReg.h | 177 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
191 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
XhciReg.h | 92 #define XHC_PORTSC_OCC BIT20 // Over-Current Change
106 #define XHC_HUB_PORTSC_PRC BIT20 // Hub's Port Reset Change
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/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
PL180Mci.h | 103 #define MCI_STATUS_CMD_TXDATAAVAILBL BIT20
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/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
BaseTypes.h | 241 #define BIT20 0x00100000
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/system/bt/embdrv/sbc/decoder/include/ |
oi_stddefs.h | 283 #define BIT20 \
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