| /device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/ |
| SP804Timer.h | 54 #define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsPcie.h | 74 #define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
|
| PchRegsPcu.h | 423 #define B_PCH_ILB_DEF0_SDD BIT21 // Sub Decode Disable
[all...] |
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 38 #undef BIT21
74 #define BIT21 0x00200000U
|
| meminit.c | 566 isbM32m(DDRPHY, (B0ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
567 isbM32m(DDRPHY, (B1ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
573 isbM32m(DDRPHY, (B0OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
574 isbM32m(DDRPHY, (B1OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
578 isbM32m(DDRPHY, (B0LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
579 isbM32m(DDRPHY, (B1LATCTL0 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // 1xCLK: tEDP, RCVEN, WDQS
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
604 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
605 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
606 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT (…)
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/ |
| Hi6220.h | 34 #define CTRL4_OTG_PHY_SEL BIT21
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530MMCHS.h | 69 #define DP_ENABLE BIT21
119 #define DCRC BIT21
132 #define DCRC_EN BIT21
147 #define DCRC_SIGEN BIT21
|
| Omap3530Dma.h | 72 #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530MMCHS.h | 69 #define DP_ENABLE BIT21
119 #define DCRC BIT21
132 #define DCRC_EN BIT21
147 #define DCRC_SIGEN BIT21
|
| Omap3530Dma.h | 72 #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
|
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| VirtioNet.h | 61 #define VIRTIO_NET_F_GUEST_ANNOUNCE BIT21 // guest can send gratuitous pkts
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 95 #define BIT21 0x00200000
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| /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/ |
| PeImage.h | 314 #define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
315 #define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
318 #define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
319 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 67 #define BIT21 0x00200000
|
| /external/syslinux/gpxe/src/include/gpxe/efi/IndustryStandard/ |
| PeImage.h | 384 #define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
385 #define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
388 #define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
389 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 119 #define INSTS_TX_IOC BIT21 // Finished loading IOC flagged buffer to Tx FIFO
215 #define MACCR_LOOPBK BIT21 // Loopback operation mode bit
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| AhciMode.h | 133 #define EFI_AHCI_PORT_CMD_ESP BIT21
174 #define EFI_AHCI_PORT_SERR_CRCE BIT21
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
| XhciReg.h | 178 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
192 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| XhciReg.h | 93 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
107 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 69 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
163 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | [all...] |
| ArmDisassembler.c | 180 W = (OpCode & BIT21) == BIT21;
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.h | 104 #define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
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| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| BaseTypes.h | 242 #define BIT21 0x00200000
|
| /system/bt/embdrv/sbc/decoder/include/ |
| oi_stddefs.h | 286 #define BIT21 \
|
