/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
PchRegsHda.h | 49 #define B_PCH_HDA_PCS_CCE BIT23 // Bus Power Control Enable, does not apply
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PchRegsLpss.h | 75 #define B_PCH_LPSS_DMAC_CLHB_MULFNDEV BIT23
160 #define B_PCH_LPSS_I2C_CLHB_MULFNDEV BIT23
247 #define B_PCH_LPSS_PWM_CLHB_MULFNDEV BIT23
334 #define B_PCH_LPSS_HSUART_CLHB_MULFNDEV BIT23
426 #define B_PCH_LPSS_SPI_CLHB_MULFNDEV BIT23
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PchRegsPcu.h | [all...] |
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
general_definitions.h | 40 #undef BIT23
76 #define BIT23 0x00800000U
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
BoardFeatures.h | 70 #define B_BOARD_FEATURES_MEMORY_SLOT_MASK BIT23 | BIT22
71 #define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT22=0, BIT23=0
72 #define V_BOARD_FEATURES_2_MEMORY_SLOT BIT22 // BIT22=1, BIT23=0
73 #define V_BOARD_FEATURES_3_MEMORY_SLOT BIT23 // BIT22=0, BIT23=1
74 #define V_BOARD_FEATURES_4_MEMORY_SLOT BIT23 | BIT22 // BIT22=1, BIT23=1
165 #define B_BOARD_FEATURES_MEMORY_SLOT_MASK (BIT24 | BIT23)
166 #define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT23=0, BIT24=0
167 #define V_BOARD_FEATURES_2_MEMORY_SLOT BIT23 // BIT23=1, BIT24=0 [all...] |
/device/linaro/bootloader/edk2/OvmfPkg/Library/AcpiTimerLib/ |
AcpiTimerLib.c | 58 while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/ |
IntelPchAcpiTimerLib.c | 109 while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
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/device/linaro/bootloader/edk2/PerformancePkg/Library/TscTimerLib/ |
TscTimerLibShare.c | 79 while (((Ticks - IoRead32 (TimerAddr)) & BIT23) == 0) {
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
CommonIncludes.h | 93 #define BIT23 0x00800000
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/device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/AcpiTimerLib/ |
AcpiTimerLib.c | 109 while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {
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/device/linaro/bootloader/edk2/MdePkg/Include/Library/ |
SmbusLib.h | 73 #define SMBUS_LIB_RESERVED(SmBusAddress) ((SmBusAddress) & ~(BIT23 - 2))
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
PchRegs.h | 69 #define BIT23 0x00800000
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/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
Lan9118DxeHw.h | 120 #define INSTS_RXDFH_INT BIT23 // Rx Dropped frames went past 0x7FFFFFFF
216 #define MACCR_RCVOWN BIT23 // Disable Receive Own frames bit
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
AhciMode.h | 107 #define EFI_AHCI_PORT_IS_IPMS BIT23
176 #define EFI_AHCI_PORT_SERR_LSE BIT23
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/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
BaseTypes.h | 244 #define BIT23 0x00800000
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/device/linaro/bootloader/edk2/PcAtChipsetPkg/Library/AcpiTimerLib/ |
AcpiTimerLib.c | 172 while (((Ticks - IoRead32 (Port)) & BIT23) == 0) {
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/system/bt/embdrv/sbc/decoder/include/ |
oi_stddefs.h | 292 #define BIT23 \
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
ThumbDisassembler.c | [all...] |
ArmDisassembler.c | 178 U = (OpCode & BIT23) == BIT23;
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/ |
MmcHostDxe.c | 272 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
311 //return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
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/device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
MmcHostDxe.c | 272 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
311 //return (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
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/bionic/libc/kernel/uapi/linux/ |
synclink.h | 46 #define BIT23 0x00800000
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/development/ndk/platforms/android-21/include/linux/ |
synclink.h | 52 #define BIT23 0x00800000
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/ |
MMCHS.c | 367 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
1102 gMMCHSMedia.ReadOnly = (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
[all...] |
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
XhciReg.h | 180 #define XHC_PORTSC_CEC BIT23 // Port Config Error Change
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