| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 45 #undef BIT28
81 #define BIT28 0x10000000U
|
| meminit.c | 558 isbM32m(DDRPHY, (B01LATCTL1 + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT4|BIT3|BIT2|BIT1|BIT0))); // Launch Time: ODT, DIFFAMP, ODT, DIFFAMP
603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
604 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
605 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
606 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
607 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT
608 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|(BIT11|BIT10|BIT9|BIT8)|BIT6|(BIT3|BIT2|BIT1|BIT0))); // Allow PUnit signals
620 isbM32m(DDRPHY, (DQVREFCH0 + (channel_i * DDRCOMP_CH_OFFSET)), ((0x08<<24)|(0x03<<16)), ((BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT21|BIT20|BIT19|BIT18|BIT17|BIT16))); // RCOMP Vref PU/PD
621 isbM32m(DDRPHY, (CMDVREFCH0 + (channel_i * DDRCOMP_CH_OFFSET)), ((0x0C<<24)|(0x03<<16)), ((BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT21|BIT20|BIT19|BIT18|BIT17|BIT16))); // RCOMP Vref PU/PD
622 isbM32m(DDRPHY, (CLKVREFCH0 + (channel_i * DDRCOMP_CH_OFFSET)), ((0x0F<<24)|(0x03<<16)), ((BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT21|BIT20|BIT19|BIT18|BIT17|BIT16))); // RCOMP Vref PU/PD
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/ |
| XPressRich3.h | 52 #define PCIE_INT_MSI BIT28
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsLpss.h | 62 #define B_PCH_LPSS_DMAC_STSCMD_RCA BIT28 // RCA
147 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
234 #define B_PCH_LPSS_PWM_STSCMD_RCA BIT28 // RCA
321 #define B_PCH_LPSS_HSUART_STSCMD_RCA BIT28 // RCA
413 #define B_PCH_LPSS_SPI_STSCMD_RCA BIT28 // RCA
|
| PchRegsPcu.h | [all...] |
| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| Virtio.h | 171 #define VIRTIO_F_RING_INDIRECT_DESC BIT28
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 88 #define BIT28 0x10000000
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 74 #define BIT28 0x10000000
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530MMCHS.h | 134 #define CERR_EN BIT28
149 #define CERR_SIGEN BIT28
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
| AhciMode.h | 111 #define EFI_AHCI_PORT_IS_HBDS BIT28
138 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530MMCHS.h | 134 #define CERR_EN BIT28
149 #define CERR_SIGEN BIT28
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 81 #define B_BOARD_FEATURES_2_SATA BIT28 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)
175 #define B_BOARD_FEATURES_HDAUDIOLINK BIT28 // HD audio link support
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 148 #define LCDENABLESIGNAL BIT28
|
| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| BaseTypes.h | 249 #define BIT28 0x10000000
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciDxe/ |
| Ehci.h | 78 #define USB_DEBUG_PORT_ENABLE BIT28
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.h | 148 #define LCDENABLESIGNAL BIT28
|
| /system/bt/embdrv/sbc/decoder/include/ |
| oi_stddefs.h | 307 #define BIT28 \
|
| /bionic/libc/kernel/uapi/linux/ |
| synclink.h | 51 #define BIT28 0x10000000
|
| /development/ndk/platforms/android-21/include/linux/ |
| synclink.h | 59 #define BIT28 0x10000000
|
| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 259 #define GPIO_LED1_ENABLE BIT28
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
| Ioh.h | 57 #define BIT28 0x10000000
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| CpuService.c | 69 ASSERT ((RegEdx & BIT28) != 0);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibPei/ |
| I2CLibPei.h | 39 #define B_PCH_LPSS_I2C_STSCMD_RCA BIT28 // RCA
|
| /external/kernel-headers/original/uapi/linux/ |
| synclink.h | 46 #define BIT28 0x10000000
|
| /external/syslinux/gpxe/src/include/gpxe/efi/ |
| Base.h | 100 #define BIT28 0x10000000
|
