/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
PchRegsRcrb.h | 46 #define B_PCH_RCRB_GCS_BBSIZE (BIT30 | BIT29) // Boot Block Size
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PchRegsPcu.h | [all...] |
/external/webrtc/webrtc/modules/audio_coding/codecs/ilbc/test/ |
iLBCtestscript.txt | 21 $EXEP/iLBCtest 30 $INP/F00.INP $OUTP/F00.BIT30 $OUTP/F00.OUT30 $INP/clean.chn 22 $EXEP/iLBCtest 30 $INP/F01.INP $OUTP/F01.BIT30 $OUTP/F01.OUT30 $INP/clean.chn 23 $EXEP/iLBCtest 30 $INP/F02.INP $OUTP/F02.BIT30 $OUTP/F02.OUT30 $INP/clean.chn 24 $EXEP/iLBCtest 30 $INP/F03.INP $OUTP/F03.BIT30 $OUTP/F03.OUT30 $INP/clean.chn 25 $EXEP/iLBCtest 30 $INP/F04.INP $OUTP/F04.BIT30 $OUTP/F04.OUT30 $INP/clean.chn 26 $EXEP/iLBCtest 30 $INP/F05.INP $OUTP/F05.BIT30 $OUTP/F05.OUT30 $INP/clean.chn 27 $EXEP/iLBCtest 30 $INP/F06.INP $OUTP/F06.BIT30 $OUTP/F06.OUT30 $INP/clean.chn 32 $EXEP/iLBCtest 30 $INP/F00.INP $OUTP/F00.BIT30 $OUTP/F00_tlm10.OUT30 $INP/tlm10.chn 33 $EXEP/iLBCtest 30 $INP/F01.INP $OUTP/F01.BIT30 $OUTP/F01_tlm10.OUT30 $INP/tlm10.chn 34 $EXEP/iLBCtest 30 $INP/F02.INP $OUTP/F02.BIT30 $OUTP/F02_tlm10.OUT30 $INP/tlm10.ch [all...] |
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
general_definitions.h | 47 #undef BIT30
83 #define BIT30 0x40000000U
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meminit.c | 603 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
604 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
605 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
606 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
607 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT
608 isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x6<<8)|BIT6|(0x4<<0)), (BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|(BIT11|BIT10|BIT9|BIT8)|BIT6|(BIT3|BIT2|BIT1|BIT0))); // Allow PUnit signals
627 isbM32m(DDRPHY, (COMPEN1CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (BIT19|BIT17), ((BIT31|BIT30)|BIT19|BIT17|(BIT15|BIT14)));
641 isbM32m(DDRPHY, (COMPEN0CH0 + (channel_i * DDRCOMP_CH_OFFSET)), (0), ((BIT31|BIT30)|BIT8)); // COMP
712 isbM32m(DDRPHY, (DQANADRVPUCTL), (BIT30), (BIT30)); // RCOMP: Dither PU Enable [all...] |
hte.c | 91 } while (0 != (isbR32m(HTE, 0x00020012) & BIT30));
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/device/linaro/bootloader/edk2/MdePkg/Library/BaseRngLib/ |
BaseRng.c | 22 #define RDRAND_MASK BIT30
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/ |
MMCHS.h | 40 #define HCS BIT30 //Host capacity support/1 = Supporting high capacity
41 #define CCS BIT30 //Card capacity status/1 = High capacity card
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/device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/ |
MMCHS.h | 40 #define HCS BIT30 //Host capacity support/1 = Supporting high capacity
41 #define CCS BIT30 //Card capacity status/1 = High capacity card
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
CommonIncludes.h | 86 #define BIT30 0x40000000
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/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
Lan9118DxeHw.h | 76 #define RXSTATUS_FILT_FAIL BIT30 // The frame failed filtering test
261 #define GPIO_LED3_ENABLE BIT30
301 #define MAC_CSR_READ BIT30
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
PchRegs.h | 76 #define BIT30 0x40000000
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/ |
AhciMode.h | 113 #define EFI_AHCI_PORT_IS_TFES BIT30
138 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
BoardFeatures.h | 83 #define B_BOARD_FEATURES_PORT80_LPC BIT30 // Port80 PCI(0) or LPC(1)
177 #define B_BOARD_FEATURES_2_SATA BIT30 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)
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/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
BaseTypes.h | 251 #define BIT30 0x40000000
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/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciDxe/ |
Ehci.h | 79 #define USB_DEBUG_PORT_OWNER BIT30
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/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
QuarkNcSocId.h | 215 #define IMR_EN BIT30
224 #define CPU_SNOOP BIT30
555 #define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30)
[all...] |
/system/bt/embdrv/sbc/decoder/include/ |
oi_stddefs.h | 313 #define BIT30 \
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/device/linaro/bootloader/edk2/ArmVirtPkg/VirtFdtDxe/ |
VirtFdtDxe.c | 122 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
127 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
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/bionic/libc/kernel/uapi/linux/ |
synclink.h | 53 #define BIT30 0x40000000
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/development/ndk/platforms/android-21/include/linux/ |
synclink.h | 61 #define BIT30 0x40000000
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/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/ |
Ioh.h | 59 #define BIT30 0x40000000
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/external/kernel-headers/original/uapi/linux/ |
synclink.h | 48 #define BIT30 0x40000000
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/external/syslinux/gpxe/src/include/gpxe/efi/ |
Base.h | 102 #define BIT30 0x40000000
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/linux/ |
synclink.h | 48 #define BIT30 0x40000000
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