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Searched
refs:BIT4
(Results
1 - 25
of
153
) sorted by null
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/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyPei/
Fdc.h
37
#define DRVA_MOTOR_ON
BIT4
// Turn On Drive A Motor
44
#define MSR_CB
BIT4
// FDC Busy
99
#define STS0_EC
BIT4
// Equipment Check
115
#define STS1_OR
BIT4
// Overrun/Underrun: Becomes set if FDC does not receive CPU or DMA service within the required time interval
130
#define STS2_WC
BIT4
// Wrong Cylinder: The track address from sector ID field is different from the track address maintained inside FDC
147
#define STS3_T0
BIT4
// Track 0
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
53
#define USBPORTSC_LSL
BIT4
// Line Status Low BIT
74
#define USBCMD_FGR
BIT4
// Force Global Resume
86
#define USBSTS_HCPE
BIT4
// Host Controller Process Error
92
#define USBTD_BABBLE
BIT4
// Babble condition
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
37
#define MCH_SMRAM_D_LCK
BIT4
44
#define MCH_ESMRAMC_SM_L1
BIT4
78
#define ICH9_GEN_PMCON_1_SMI_LOCK
BIT4
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530Usb.h
37
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE
BIT4
Omap3530I2c.h
22
#define XRDY_IE
BIT4
29
#define XRDY
BIT4
Omap3530MMCHS.h
39
#define MODE
BIT4
60
#define DDIR_READ
BIT4
114
#define BWR
BIT4
125
#define BWR_EN
BIT4
140
#define BWR_SIGEN
BIT4
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530Usb.h
37
#define UHH_HOSTCONFIG_ENA_INCR16_ENABLE
BIT4
Omap3530I2c.h
22
#define XRDY_IE
BIT4
29
#define XRDY
BIT4
Omap3530MMCHS.h
39
#define MODE
BIT4
60
#define DDIR_READ
BIT4
114
#define BWR
BIT4
125
#define BWR_EN
BIT4
140
#define BWR_SIGEN
BIT4
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
39
#define CTRL5_PICOPHY_ACAENB
BIT4
56
#define RST0_USBOTG_BUS
BIT4
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
51
#define B_I2C_REG_CON_10BITADD_MASTER (
BIT4
) // 7-bit addressing (0) or 10-bit addressing (1)
53
#define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+
BIT4
+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsSata.h
73
#define B_PCH_SATA_COMMAND_PMWE
BIT4
// Memory Write and Invalidate Enable
87
#define B_PCH_SATA_PCISTS_CAP_LIST
BIT4
// Capabilities List
133
#define B_PCH_SATA_LBAR_BA4
BIT4
// Base Address 4
195
#define B_PCH_SATA_PCS_PORT4_EN
BIT4
// Port 4 Enabled
204
#define B_PCH_SATA_PORT4_IMPLEMENTED
BIT4
// Port 4 Implemented
PchRegsPcu.h
81
#define B_PCH_LPC_COMMAND_MWIE
BIT4
// Memory Write and Invalidate Enable
97
#define B_PCH_LPC_DEV_STS_CAP_LIST
BIT4
// Capabilities List
373
#define B_PCH_ILB_DXXIR_IBR_MASK (BIT6 | BIT5 |
BIT4
) // INTB Mask
375
#define V_PCH_ILB_DXXIR_IBR_PIRQB
BIT4
// INTB Mapping to IRQ B
377
#define V_PCH_ILB_DXXIR_IBR_PIRQD (BIT5 |
BIT4
) // INTB Mapping to IRQ D
379
#define V_PCH_ILB_DXXIR_IBR_PIRQF (BIT6 |
BIT4
) // INTB Mapping to IRQ F
381
#define V_PCH_ILB_DXXIR_IBR_PIRQH (BIT6 | BIT5 |
BIT4
) // INTB Mapping to IRQ H
415
#define B_PCH_ILB_RTCC_RTCB2
BIT4
// RTC Bias Resistor 2, Adds 120 Kohm
430
#define B_PCH_ILB_DEF1_FOAR
BIT4
// 8254 Freeze_On_AnyRead
442
#define B_PCH_ILB_GNMI_NMIN
BIT4
// NMI NOW
[
all
...]
PchRegsPcie.h
81
#define B_PCH_PCIE_SLCTL_SLSTS_CCE
BIT4
// Command Completed Interrupt Enable
PchRegsSpi.h
50
#define B_PCH_SPI_HSFS_BERASE_MASK (
BIT4
| BIT3) // Block / Sector Erase Size
81
#define B_PCH_SPI_OPTYPE2_MASK (BIT5 |
BIT4
) // Opcode Type 2 Mask
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/
Isp1761UsbDxe.h
46
#define ISP1761_DC_INTERRUPT_RESUME
BIT4
64
#define ISP1761_MODE_SFRESET
BIT4
70
#define ISP1761_ENDPOINT_TYPE_NOEMPKT
BIT4
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
61
#define I2C_INTR_TX_EMPTY
BIT4
86
#define STAT_RFF
BIT4
// RX FIFO is completely full
121
#define I2C_INTR_TX_EMPTY
BIT4
/device/linaro/bootloader/edk2/IntelFspPkg/Library/BaseCacheLib/
CacheLibInternal.h
53
#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 |
BIT4
| BIT3 | BIT2 | BIT1 | BIT0)
/device/linaro/bootloader/edk2/SecurityPkg/Include/Library/
Tcg2PhysicalPresenceLib.h
30
#define TCG2_BIOS_TPM_MANAGEMENT_FLAG_PP_REQUIRED_FOR_TURN_ON
BIT4
TpmCommLib.h
143
#define TIS_PC_ACC_SEIZED
BIT4
175
#define TIS_PC_STS_DATA
BIT4
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
HdLcd.h
67
#define HDLCD_BURST_16
BIT4
74
#define HDLCD_PXCLK_HIGH
BIT4
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
21
#undef
BIT4
57
#define
BIT4
0x00000010U
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
94
#define EPHSR_16COL
BIT4
120
#define RPCR_LS2B
BIT4
146
#define CTR_RESERVED (BIT12 | BIT9 |
BIT4
)
187
#define IST_RX_OVRN
BIT4
259
#define PHYSTS_REMOTE_FAULT
BIT4
// Remote fault detected
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
72
#define I2C_INTR_TX_EMPTY
BIT4
97
#define STAT_RFF
BIT4
// RX FIFO is completely full
134
#define I2C_INTR_TX_EMPTY
BIT4
/device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/
IsaFloppy.h
209
#define DRVA_MOTOR_ON
BIT4
232
#define MSR_CB
BIT4
343
#define STS0_EC
BIT4
389
#define STS1_OR
BIT4
423
#define STS2_WC
BIT4
443
#define STS3_T0
BIT4
Completed in 1855 milliseconds
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