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Searched
refs:BIT9
(Results
1 - 25
of
121
) sorted by null
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
Omap3530.h
37
#define PBIASLITEWRDNZ1
BIT9
Omap3530Dma.h
92
#define DMA4_CCR_RD_ACTIVE
BIT9
118
#define DMA4_CSR_SECURE_ERR
BIT9
Omap3530I2c.h
45
#define TRX
BIT9
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
Omap3530.h
37
#define PBIASLITEWRDNZ1
BIT9
Omap3530Dma.h
92
#define DMA4_CCR_RD_ACTIVE
BIT9
118
#define DMA4_CSR_SECURE_ERR
BIT9
Omap3530I2c.h
45
#define TRX
BIT9
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
I2cRegs.h
53
#define B_I2C_REG_TAR (
BIT9
+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) // Master Target Address bits
56
#define B_I2C_REG_DATA_CMD_STOP (
BIT9
) // Data Buffer and Command Register STOP bit
63
#define B_I2C_REG_INTR_STAT_STOP_DET (
BIT9
) // Interrupt Status Register STOP_DET signal status
66
#define I2C_REG_RAW_INTR_STAT_STOP_DET (
BIT9
) // Raw Interrupt Status Register STOP_DET signal status.
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
PchRegsUsb.h
70
#define B_PCH_EHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 |
BIT9
) // Data Select
93
#define B_PCH_XHCI_PWR_CNTL_STS_DATASEL (BIT12 | BIT11 | BIT10 |
BIT9
)
PchRegsSata.h
68
#define B_PCH_SATA_COMMAND_FBE
BIT9
// Fast Back-to-back Enable
85
#define B_PCH_SATA_PCISTS_DEV_STS_MASK (BIT10 |
BIT9
) // DEVSEL# Timing Status
170
#define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 |
BIT9
| BIT8) // SATA Port Disable
176
#define B_PCH_SATA_PORT1_DISABLED
BIT9
192
#define B_PCH_SATA_PCS_PORT1_DET
BIT9
// Port 1 Present
PchRegsPcu.h
76
#define B_PCH_LPC_COMMAND_FBE
BIT9
// Fast Back to Back Enable
93
#define B_PCH_LPC_DEV_STS_DEVT_STS (BIT10 |
BIT9
) // DEVSEL# Timing Status
201
#define B_PCH_LPC_FWH_BIOS_DEC_EC8
BIT9
// C8-CF Enable
241
#define B_PCH_LPC_CGC_SBLCG
BIT9
// IOSF-SB Local Clock Gating Disable
296
#define B_PCH_ILB_ULKMC_TRAPBY60W
BIT9
// SMI Caused by Port 60 Write
363
#define B_PCH_ILB_DXXIR_ICR_MASK (BIT10 |
BIT9
| BIT8) // INTC Mask
366
#define V_PCH_ILB_DXXIR_ICR_PIRQC
BIT9
// INTC Mapping to IRQ C
367
#define V_PCH_ILB_DXXIR_ICR_PIRQD (
BIT9
| BIT8) // INTC Mapping to IRQ D
370
#define V_PCH_ILB_DXXIR_ICR_PIRQG (BIT10 |
BIT9
) // INTC Mapping to IRQ G
371
#define V_PCH_ILB_DXXIR_ICR_PIRQH (BIT10 |
BIT9
| BIT8) // INTC Mapping to IRQ H
[
all
...]
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Library/I2CLibDxe/
I2CRegs.h
43
#define B_CMD_STOP
BIT9
// 1 = STOP
58
#define I2C_INTR_STOP_DET
BIT9
118
#define I2C_INTR_STOP_DET
BIT9
/device/linaro/bootloader/edk2/SecurityPkg/Include/Library/
Tcg2PhysicalPresenceLib.h
39
#define TCG2_BIOS_INFORMATION_FLAG_HIERACHY_CONTROL_ENDORSEMENT_DISABLE
BIT9
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
general_definitions.h
26
#undef
BIT9
62
#define
BIT9
0x00000200U
/device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/
Lan91xDxeHw.h
98
#define EPHSR_LATCOL
BIT9
109
#define RCR_STRIP_CRC
BIT9
129
#define CR_EXT_PHY
BIT9
146
#define CTR_RESERVED (BIT12 |
BIT9
| BIT4)
247
#define PHYCR_RST_AUTO
BIT9
// Restart Auto-Negotiation of Link abilities
274
#define PHYANA_100BASET4
BIT9
// Advertise 100 BASETX Full duplex capability
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
Lan9118DxeHw.h
83
#define TXSTATUS_LCOLL
BIT9
// Packet Tx aborted after coll window of 64 bytes
109
#define INSTS_TDFA
BIT9
// Tx Data FIFO Level exceeded
143
#define MPTCTRL_WOL_EN
BIT9
// Enable wake-on-lan
150
#define PHYCR_RST_AUTO
BIT9
// Restart Auto-Negotiation of Link abilities
224
#define WUCSR_GUE
BIT9
// Enable wake on global unicast frames
251
#define E2P_EPC_TIMEOUT
BIT9
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
PL180Mci.h
79
#define MCI_CLOCK_POWERSAVE
BIT9
92
#define MCI_STATUS_CMD_START_BIT_ERROR
BIT9
145
#define MCI_CPSM_LONG_PENDING
BIT9
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Library/
I2CLib.h
54
#define B_CMD_STOP
BIT9
// 1 = STOP
69
#define I2C_INTR_STOP_DET
BIT9
131
#define I2C_INTR_STOP_DET
BIT9
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
Hi6220.h
44
#define CTRL5_PICOPHY_DCDENB
BIT9
/device/linaro/bootloader/edk2/OptionRomPkg/Bus/Usb/FtdiUsbSerialDxe/
FtdiUsbSerialDriver.h
119
#define SET_PARITY_EVEN
BIT9
// (0x2 << 8)
120
#define SET_PARITY_MARK
BIT9
| BIT8 // (0x3 << 8)
137
#define SET_RTS_HIGH (
BIT9
| BIT1)
138
#define SET_RTS_LOW (
BIT9
)
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
Q35MchIch9.h
72
BIT10 |
BIT9
| BIT8 | BIT7)
VirtioBlk.h
61
#define VIRTIO_BLK_F_FLUSH
BIT9
// identical to "write cache enabled"
VirtioNet.h
50
#define VIRTIO_NET_F_GUEST_ECN
BIT9
// guest can receive TSO with ECN
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
struct.s
34
BIT9
.field 9 ;
bit9
= 64
/device/linaro/bootloader/edk2/ShellPkg/Include/Library/
HandleParsingLib.h
151
#define HR_PARENT_HANDLE
BIT9
154
#define HR_VALID_MASK (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6|BIT7|BIT8|
BIT9
|BIT10|BIT11)
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
UhciReg.h
57
#define USBPORTSC_PR
BIT9
// Port Reset
Completed in 1446 milliseconds
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