| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 80 unsigned BasePtr;
81 int64_t Offset = (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr) +
86 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
101 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
124 MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
132 .addReg(BasePtr).addImm(HighOffset).addReg(0);
138 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
|
| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 72 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
77 BasePtr = X86::ESI;
462 unsigned BasePtr = getX86SubSuperRegister(getBaseRegister(), 64);
463 for (MCSubRegIterator I(BasePtr, this, /*IncludeSelf=*/true);
563 return MRI->canReserveReg(BasePtr);
582 unsigned BasePtr;
589 BasePtr = (FrameIndex < 0 ? FramePtr : getBaseRegister());
591 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
593 BasePtr = StackPtr;
595 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr)
[all...] |
| X86RegisterInfo.h | 47 /// BasePtr - X86 physical register used as a base ptr in complex stack
50 unsigned BasePtr;
135 unsigned getBaseRegister() const { return BasePtr; }
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCLoopPreIncPrep.cpp | 123 static bool IsPtrInBounds(Value *BasePtr) {
124 Value *StrippedBasePtr = BasePtr;
314 Value *BasePtr = GetPointerOperand(MemI);
315 assert(BasePtr && "No pointer operand");
319 BasePtr->getType()->getPointerAddressSpace());
357 PtrInc->setIsInBounds(IsPtrInBounds(BasePtr));
367 if (PtrInc->getType() != BasePtr->getType())
368 NewBasePtr = new BitCastInst(PtrInc, BasePtr->getType(),
373 if (Instruction *IDel = dyn_cast<Instruction>(BasePtr))
375 BasePtr->replaceAllUsesWith(NewBasePtr)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 116 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FP : MSP430::SP);
137 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
154 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 111 unsigned BasePtr = (TFI->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
114 // FrameIndex with base register with BasePtr. Add an offset to the
116 MI.getOperand(i).ChangeToRegister(BasePtr, false);
|
| /external/webrtc/webrtc/voice_engine/test/auto_test/ |
| voe_stress_test.cc | 120 VoEBase* base = _mgr.BasePtr();
195 VoEBase* base = _mgr.BasePtr();
305 VoEBase* base = _mgr.BasePtr();
388 VoEBase* base = _mgr.BasePtr();
|
| voe_output_test.cc | 80 VoEBase* base = manager_.BasePtr();
117 VoEBase* base = manager_.BasePtr();
|
| voe_cpu_test.cc | 48 VoEBase* base = _mgr.BasePtr();
|
| voe_standard_test.h | 137 VoEBase* BasePtr() const {
|
| /external/llvm/lib/CodeGen/ |
| ShadowStackGCLowering.cpp | 60 Type *Ty, Value *BasePtr, int Idx1,
63 Type *Ty, Value *BasePtr, int Idx1, int Idx2,
355 Value *BasePtr, int Idx,
361 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name);
369 IRBuilder<> &B, Type *Ty, Value *BasePtr,
373 Value *Val = B.CreateGEP(Ty, BasePtr, Indices, Name);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ShadowStackGC.cpp | 67 IRBuilder<> &B, Value *BasePtr,
70 IRBuilder<> &B, Value *BasePtr,
350 ShadowStackGC::CreateGEP(LLVMContext &Context, IRBuilder<> &B, Value *BasePtr,
355 Value* Val = B.CreateGEP(BasePtr, Indices, Name);
363 ShadowStackGC::CreateGEP(LLVMContext &Context, IRBuilder<> &B, Value *BasePtr,
367 Value *Val = B.CreateGEP(BasePtr, Indices, Name);
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 87 /// BasePtr - ARM physical register used as a base ptr in complex stack
90 unsigned BasePtr;
162 unsigned getBaseRegister() const { return BasePtr; }
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 83 /// BasePtr - ARM physical register used as a base ptr in complex stack
86 unsigned BasePtr;
157 unsigned getBaseRegister() const { return BasePtr; }
|
| Thumb1FrameLowering.cpp | 62 unsigned BasePtr = RegInfo->getBaseRegister();
168 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/ |
| builder_misc.h | 82 LoadInst *LOAD(Value *BasePtr, const std::initializer_list<uint32_t> &offset, const llvm::Twine& name = "");
83 LoadInst *LOADV(Value *BasePtr, const std::initializer_list<Value*> &offset, const llvm::Twine& name = "");
84 StoreInst *STORE(Value *Val, Value *BasePtr, const std::initializer_list<uint32_t> &offset);
85 StoreInst *STOREV(Value *Val, Value *BasePtr, const std::initializer_list<Value*> &offset);
|
| /device/linaro/bootloader/edk2/DuetPkg/DxeIpl/ |
| LegacyTable.c | 160 UINTN BasePtr;
167 BasePtr = (UINTN)(&(Xsdt->Entry));
169 CopyMem (&EntryPtr, (VOID *)(BasePtr + Index * sizeof(UINT64)), sizeof(UINT64));
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 181 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW);
201 MI.getOperand(i).ChangeToRegister(BasePtr, false);
218 MI.getOperand(i).ChangeToRegister(BasePtr, false);
|
| /device/linaro/bootloader/edk2/OvmfPkg/AcpiS3SaveDxe/ |
| AcpiS3Save.c | 139 UINTN BasePtr;
148 BasePtr = (UINTN)(Xsdt + 1);
150 CopyMem (&EntryPtr, (VOID *)(BasePtr + Index * sizeof(UINT64)), sizeof(UINT64));
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| LoopIdiomRecognize.cpp | 483 Value *BasePtr =
488 if (mayLoopAccessLocation(BasePtr, AliasAnalysis::ModRef,
493 deleteIfDeadInstruction(BasePtr, *SE);
515 NewCall = Builder.CreateMemSet(BasePtr, SplatValue,NumBytes,StoreAlignment);
532 NewCall = Builder.CreateCall3(MSP, BasePtr, PatternPtr, NumBytes);
|
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/ |
| AcpiS3Save.c | 165 UINTN BasePtr;
174 BasePtr = (UINTN)(Xsdt + 1);
176 CopyMem (&EntryPtr, (VOID *)(BasePtr + Index * sizeof(UINT64)), sizeof(UINT64));
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 438 SDValue BasePtr = LD->getBasePtr();
444 if (DAG.isBaseWithConstantOffset(BasePtr) &&
445 isWordAligned(BasePtr->getOperand(0), DAG)) {
446 SDValue NewBasePtr = BasePtr->getOperand(0);
447 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
451 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
454 BasePtr->getValueType(0));
462 BasePtr, LD->getPointerInfo(), MVT::i16,
465 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
481 // Lower to a call to __misaligned_load(BasePtr)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 408 SDValue BasePtr = LD->getBasePtr();
414 IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
419 return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
452 BasePtr, LD->getPointerInfo(), MVT::i16,
454 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
470 // Lower to a call to __misaligned_load(BasePtr).
476 Entry.Node = BasePtr;
508 SDValue BasePtr = ST->getBasePtr();
516 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
520 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
[all...] |
