| /external/mesa3d/src/egl/main/ |
| eglcompiler.h | 37 #define STATIC_ASSERT(COND) \
39 (void) sizeof(char [1 - 2*!(COND)]); \
|
| /external/libopus/silk/ |
| typedef.h | 57 # define silk_assert(COND) _ASSERTE(COND)
72 # define silk_assert(COND) {if (!(COND)) {silk_fatal("assertion failed: " #COND);}}
74 # define silk_assert(COND)
|
| /external/skia/include/gpu/ |
| GrConfig.h | 144 #define GR_ALWAYSASSERT(COND) \
146 if (!(COND)) { \
147 SkDebugf("%s %s failed\n", GR_FILE_AND_LINE_STR, #COND); \
158 #define GR_DEBUGASSERT(COND) GR_ALWAYSASSERT(COND)
160 #define GR_DEBUGASSERT(COND)
167 #define GrAlwaysAssert(COND) GR_ALWAYSASSERT(COND)
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_asm.c | 72 VIV_ISA_WORD_0_COND(inst->cond) |
73 COND(inst->sat, VIV_ISA_WORD_0_SAT) |
74 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) |
81 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) |
83 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) |
85 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) |
86 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS);
89 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) |
92 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) |
93 COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS)
[all...] |
| etnaviv_rs.c | 45 unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2);
46 unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2);
49 int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
50 int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
61 COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) |
62 COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) |
63 COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) |
65 COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) |
66 COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) |
67 COND(rs->flip, VIVS_RS_CONFIG_FLIP)
[all...] |
| etnaviv_rasterizer.c | 57 COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) |
58 COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) |
59 COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE);
64 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE);
68 COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4);
|
| etnaviv_zsa.c | 98 COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) |
99 COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) |
100 COND(disable_zs, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS);
102 COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) |
|
| etnaviv_blend.c | 75 COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) |
88 COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE);
|
| etnaviv_util.h | 31 #define COND(bool, val) ((bool) ? (val) : 0)
|
| /external/chromium-trace/catapult/systrace/atrace_helper/jni/ |
| logging.h | 12 #define CHECK_ARGS(COND, ERR) \
13 "FAILED CHECK(%s) @ %s:%d (errno: %s)\n", #COND, __FILE__, __LINE__, \
|
| /system/bt/osi/include/ |
| osi.h | 43 #define COMPILE_ASSERT(COND) \
44 typedef int failed_compile_assert[(COND) ? 1 : -1] __attribute__((unused))
|
| /external/libdrm/ |
| libdrm_macros.h | 35 * Basically, use COND to dimension an array. If COND is false/zero the
38 #define STATIC_ASSERT(COND) \
40 (void) sizeof(char [1 - 2*!(COND)]); \
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 40 #define COND(_a) gCondition[((_a) >> 28)]
198 // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
199 AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
201 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
202 AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
210 // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
211 // A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
212 // A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
213 AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (W), MRegList (OpCode), USER (B));
215 // A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| fd4_program.c | 319 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
323 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
324 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
325 COND(s[VS].instrlen && s[FS].instrlen,
338 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
388 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
407 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
413 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
416 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
417 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING)
[all...] |
| fd4_blend.c | 120 COND(cso->logicop_enable, A4XX_RB_MRT_CONTROL_ROP_ENABLE) |
141 COND(cso->independent_blend_enable, A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND);
|
| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| fd5_program.c | 231 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) |
232 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) |
233 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) |
234 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3));
380 COND(s[VS].v, A5XX_HLSQ_VS_CONTROL_REG_ENABLED));
383 COND(s[FS].v, A5XX_HLSQ_FS_CONTROL_REG_ENABLED));
386 COND(s[HS].v, A5XX_HLSQ_HS_CONTROL_REG_ENABLED));
389 COND(s[DS].v, A5XX_HLSQ_DS_CONTROL_REG_ENABLED));
392 COND(s[GS].v, A5XX_HLSQ_GS_CONTROL_REG_ENABLED));
407 COND(s[VS].v, A5XX_SP_VS_CONTROL_REG_ENABLED))
[all...] |
| fd5_emit.h | 117 OUT_RING(ring, COND(mode == GMEM, CP_SET_RENDER_MODE_3_GMEM_ENABLE));
152 COND(!blit, 0x8));
|
| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| fd3_program.c | 242 COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) |
255 COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
265 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
334 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
340 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
356 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
363 COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
367 mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
368 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
377 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE))
[all...] |
| fd3_rasterizer.c | 69 COND(cso->clip_halfz, A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z);
|
| /toolchain/binutils/binutils-2.25/binutils/ |
| syslex.l | 84 "cond" { return COND;}
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| arc-opc.c | 141 'q' COND condition code field
240 #define COND (DELAY + 1)
244 #define FORCELIMM (COND + 1)
1225 long cond; local
[all...] |
| frv-opc.c | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
| anames7.go | 17 "COND",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
| anames7.go | 17 "COND",
|
| /external/valgrind/drd/tests/ |
| tsan_unittest.cpp | 33 // with any other library that supports threads, locks, cond vars, etc.
132 int COND = 0;
367 // 1. COND = 0
371 // c. COND = 1
373 // 4. while(COND) / e. MU.Unlock()
384 COND = 1;
392 COND = 0;
395 while(COND != 1)
416 // 1. COND = 0
420 // c. COND =
[all...] |
