| /external/vixl/tools/ |
| verify_assembler_traces.py | 43 For example, let's say we have the following assembler trace for CLZ
48 0x10, 0x0f, 0x6f, 0x01 // Clz eq r0 r0
51 0x11, 0x0f, 0x6f, 0x01 // Clz eq r0 r1
54 0x12, 0x0f, 0x6f, 0x01 // Clz eq r0 r2
79 ("Clz eq r0 r0", ["0x10", "0x0f", "0x6f", "0x01"]),
80 ("Clz eq r0 r1", ["0x11", "0x0f", "0x6f", "0x01"]),
81 ("Clz eq r0 r2", ["0x12", "0x0f", "0x6f", "0x01"])
331 ("Clz eq r0 r0", ["0x10", "0x0f", "0x6f", "0x01"]),
332 ("Clz eq r0 r1", ["0x11", "0x0f", "0x6f", "0x01"]),
333 ("Clz eq r0 r2", ["0x12", "0x0f", "0x6f", "0x01"]
[all...] |
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| OpenCL.std.h | 201 Clz = 151,
|
| SPIRVExtInst.h | 212 add(OpenCLLIB::Clz, "clz");
|
| /prebuilts/ndk/r13/sources/third_party/shaderc/third_party/spirv-tools/external/spirv-headers/include/spirv/1.0/ |
| OpenCL.std.h | 201 Clz = 151,
|
| /prebuilts/ndk/r13/sources/third_party/shaderc/third_party/spirv-tools/external/spirv-headers/include/spirv/1.1/ |
| OpenCL.std.h | 201 Clz = 151,
|
| /external/v8/src/wasm/ |
| wasm-opcodes.cc | 66 CASE_INT_OP(Clz, "clz")
|
| /art/compiler/optimizing/ |
| intrinsics_arm_vixl.cc | 357 __ Clz(out, in_reg_hi);
359 __ Clz(out, in_reg_lo);
365 __ Clz(out, RegisterFrom(in));
404 __ Clz(out, out);
407 __ Clz(out, out);
415 __ Clz(out, out);
[all...] |
| intrinsics_arm64.cc | 366 __ Clz(RegisterFrom(out, type), RegisterFrom(in, type));
394 __ Clz(RegisterFrom(out, type), RegisterFrom(out, type));
[all...] |
| intrinsics_mips64.cc | 285 __ Clz(out, in);
322 __ Clz(out.AsRegister<GpuRegister>(), out.AsRegister<GpuRegister>());
[all...] |
| /external/v8/src/compiler/ |
| machine-operator.h | 643 V(Word, Clz) \
|
| /external/swiftshader/third_party/subzero/src/ |
| IceInstARM32.h | 388 Clz,
[all...] |
| IceInstMIPS32.h | 214 Clz,
[all...] |
| /external/vixl/test/aarch32/ |
| test-macro-assembler-cond-rd-rn-a32.cc | 56 M(Clz) \
[all...] |
| test-macro-assembler-cond-rd-rn-t32.cc | 56 M(Clz) \
[all...] |
| test-disasm-a32.cc | [all...] |
| test-simulator-cond-rd-rn-a32.cc | 118 M(Clz) \
[all...] |
| test-simulator-cond-rd-rn-t32.cc | 118 M(Clz) \
[all...] |
| /external/v8/src/compiler/arm64/ |
| code-generator-arm64.cc | [all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 438 void MacroAssembler::Clz(const Register& rd, const Register& rn) {
441 clz(rd, rn);
[all...] |
| macro-assembler-arm64.h | 369 inline void Clz(const Register& rd, const Register& rn);
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | [all...] |
| assembler_mips64.h | 538 void Clz(GpuRegister rd, GpuRegister rs);
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.h | [all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.h | 314 void Clz(Register rd, Register rs);
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.h | 347 void Clz(Register rd, Register rs);
[all...] |
