| /external/llvm/lib/CodeGen/ |
| EarlyIfConversion.cpp | 114 int CondCycles, TCycles, FCycles;
117 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
424 PI.CondCycles, PI.TCycles, PI.FCycles)) {
734 unsigned CondDepth = adjCycles(BranchDepth, PI.CondCycles);
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 677 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
685 /// @param CondCycles Latency from Cond+Branch to select output.
691 int &CondCycles,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 683 /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
691 /// @param CondCycles Latency from Cond+Branch to select output.
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 688 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
718 CondCycles = 1;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
385 CondCycles = 1 + ExtraCondLat;
398 CondCycles = 5 + ExtraCondLat;
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
