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    Searched refs:DestRC (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/Target/NVPTX/
NVPTXInstrInfo.cpp 38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
41 if (DestRC->getSize() != SrcRC->getSize())
45 if (DestRC == &NVPTX::Int1RegsRegClass) {
47 } else if (DestRC == &NVPTX::Int16RegsRegClass) {
49 } else if (DestRC == &NVPTX::Int32RegsRegClass) {
52 } else if (DestRC == &NVPTX::Int64RegsRegClass) {
55 } else if (DestRC == &NVPTX::Float32RegsRegClass) {
58 } else if (DestRC == &NVPTX::Float64RegsRegClass) {
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
ScheduleDAGFast.cpp 381 const TargetRegisterClass *DestRC,
386 CopyFromSU->CopyDstRC = DestRC;
389 CopyToSU->CopySrcRC = DestRC;
572 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
582 if (DestRC != RC) {
584 if (!DestRC && !NewDef)
591 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
ScheduleDAGRRList.cpp     [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGFast.cpp 388 const TargetRegisterClass *DestRC,
393 CopyFromSU->CopyDstRC = DestRC;
396 CopyToSU->CopySrcRC = DestRC;
583 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
593 if (DestRC != RC) {
595 if (!DestRC && !NewDef)
602 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
ScheduleDAGRRList.cpp     [all...]
  /external/llvm/lib/Target/AMDGPU/
SIFoldOperands.cpp 238 const TargetRegisterClass *DestRC
243 unsigned MovOp = TII->getMovOpcode(DestRC);
SIInstrInfo.cpp     [all...]

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