| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/ |
| reg-op.s | 9 FSUB X,$38,$212
|
| reg-op.l | 12 9 0018 061726D4 FSUB X,\$38,\$212
|
| list-insns.s | 26 FSUB $112,$223,$41
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| floatdp2.s | 29 .irp op, FMUL, FDIV, FADD, FSUB, FMAX, FMIN, FMAXNM, FMINNM, FNMUL
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/ |
| blend_jit.cpp | 79 out[0] = out[1] = out[2] = VMINPS(src[3], FSUB(VIMMED1(1.0f), dst[3]));
104 out[0] = FSUB(VIMMED1(1.0f), src[0]);
105 out[1] = FSUB(VIMMED1(1.0f), src[1]);
106 out[2] = FSUB(VIMMED1(1.0f), src[2]);
107 out[3] = FSUB(VIMMED1(1.0f), src[3]);
110 out[0] = out[1] = out[2] = out[3] = FSUB(VIMMED1(1.0f), src[3]);
113 out[0] = out[1] = out[2] = out[3] = FSUB(VIMMED1(1.0f), dst[3]);
116 out[0] = FSUB(VIMMED1(1.0f), dst[0]);
117 out[1] = FSUB(VIMMED1(1.0f), dst[1]);
118 out[2] = FSUB(VIMMED1(1.0f), dst[2])
[all...] |
| /external/javassist/src/main/javassist/bytecode/ |
| Opcode.java | 110 int FSUB = 102;
346 -1, // fsub, 102
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
147 case ISD::FSUB:
340 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
342 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM,
[all...] |
| /prebuilts/go/darwin-x86/src/math/ |
| dim_s390x.s | 35 FSUB F2, F1
|
| /prebuilts/go/linux-x86/src/math/ |
| dim_s390x.s | 35 FSUB F2, F1
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| m88k-dis.c | 183 {0x84003000,"fsub.sss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {5,1,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,0,0} },
184 {0x84003080,"fsub.ssd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,0,1,0} },
185 {0x84003200,"fsub.sds ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,0,0} },
186 {0x84003280,"fsub.sdd ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,0,1,1,0} },
187 {0x84003020,"fsub.dss ",{21,5,REG} ,{16,5,REG} ,{0,5,REG} , {6,2,PFLT,FSUB ,0,1,1,1,0,0,0,1,1,0,0,0} }
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 241 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUTargetTransformInfo.cpp | 165 case ISD::FSUB:
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| vc4_qpu.h | 195 A_ALU2(FSUB)
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 246 FADD, FSUB, FMUL, FDIV, FREM,
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| m88k.h | 343 #define FSUB NOP +2
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
| gnu.go | 22 case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP:
23 // DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least
36 case FSUB:
39 inst.Op = FSUB
914 case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR:
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/x86/x86asm/ |
| gnu.go | 22 case FDIV, FDIVR, FSUB, FSUBR, FDIVP, FDIVRP, FSUBP, FSUBRP:
23 // DC E0, DC F0: libopcodes swaps FSUBR/FSUB and FDIVR/FDIV, at least
36 case FSUB:
39 inst.Op = FSUB
914 case FADD, FCOM, FCOMP, FDIV, FDIVR, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FMUL, FST, FSTP, FSUB, FSUBR:
|
