| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 242 const HexagonRegisterInfo &HRI) {
271 for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
346 auto &HRI = *HST.getRegisterInfo();
377 for (const MCPhysReg *P = HRI.getCalleeSavedRegs(&MF); *P; ++P)
378 for (MCSubRegIterator S(*P, &HRI, true); S.isValid(); ++S)
382 if (needsStackFrame(I, CSR, HRI))
444 auto &HRI = *HST.getRegisterInfo();
454 insertCSRSpillsInBlock(*PrologB, CSI, HRI, PrologueStubs);
458 insertCSRRestoresInBlock(*EpilogB, CSI, HRI);
463 insertCSRRestoresInBlock(B, CSI, HRI);
[all...] |
| HexagonVLIWPacketizer.cpp | 89 const HexagonRegisterInfo *HRI;
110 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
178 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
271 if (DepReg == HRI->getRARegister())
275 if (DepReg == HRI->getFrameRegister() || DepReg == HRI->getStackRegister())
279 const TargetRegisterClass* RC = HRI->getMinimalPhysRegClass(DepReg);
544 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
594 predRegClass = HRI->getMinimalPhysRegClass(predRegNumSrc);
606 predRegClass = HRI->getMinimalPhysRegClass(predRegNumDst)
[all...] |
| HexagonInstrInfo.cpp | 114 static bool isDblRegForSubInst(unsigned Reg, const HexagonRegisterInfo &HRI) {
115 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) &&
116 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg));
764 auto &HRI = getRegisterInfo();
826 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag)
827 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag);
847 unsigned DstHi = HRI.getSubReg(DestReg, Hexagon::subreg_hireg);
849 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), KillFlag);
850 unsigned DstLo = HRI.getSubReg(DestReg, Hexagon::subreg_loreg);
852 .addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), KillFlag)
[all...] |
| HexagonBranchRelaxation.cpp | 58 const HexagonRegisterInfo *HRI;
85 HRI = HST.getRegisterInfo();
|
| HexagonGenMux.cpp | 42 HexagonGenMux() : MachineFunctionPass(ID), HII(0), HRI(0) {
59 const HexagonRegisterInfo *HRI;
109 for (MCSubRegIterator I(Reg, HRI); I.isValid(); ++I)
148 unsigned NR = HRI->getNumRegs();
315 HRI = MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
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| HexagonRDFOpt.cpp | 282 const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
289 HexagonRegisterAliasInfo HAI(HRI);
291 DataFlowGraph G(MF, HII, HRI, *MDT, MDF, HAI, TOI);
|
| HexagonVLIWPacketizer.h | 41 const HexagonRegisterInfo *HRI;
|
| HexagonGenInsert.cpp | 467 HexagonGenInsert() : MachineFunctionPass(ID), HII(0), HRI(0) {
523 const HexagonRegisterInfo *HRI;
542 dbgs() << " " << PrintReg(I->first, HRI) << ":\n";
545 dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
546 << PrintRegSet(LL[i].second, HRI) << '\n';
760 dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI)
761 << " AVs: " << PrintORL(AVs, HRI) << "\n";
824 dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n";
829 dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@"
877 dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI
[all...] |
| HexagonFrameLowering.h | 91 const HexagonRegisterInfo &HRI, bool &PrologueStubs) const;
93 const HexagonRegisterInfo &HRI) const;
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| HexagonBitSimplify.cpp | [all...] |
| HexagonISelLowering.cpp | 725 auto &HRI = *Subtarget.getRegisterInfo();
727 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
[all...] |
| HexagonISelDAGToDAG.cpp | 48 const HexagonRegisterInfo *HRI;
53 HRI(nullptr) {}
59 HRI = HST->getRegisterInfo();
[all...] |
