| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 783 unsigned HiReg = HiOperand.getReg();
791 .addReg(HiReg, HiRegKillFlag)
799 .addReg(HiReg, HiRegKillFlag)
821 // DoubleRegDest = combine HiReg, #LoImm
823 .addReg(HiReg, HiRegKillFlag)
834 unsigned HiReg = HiOperand.getReg();
840 // DoubleRegDest = combine HiReg, LoReg
842 .addReg(HiReg, HiRegKillFlag)
|
| HexagonFrameLowering.cpp | 205 bool hireg = true) {
211 if (hireg) {
826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg);
828 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
696 .addReg(HiReg);
701 .addReg(HiReg);
|
| MipsSEFrameLowering.cpp | 285 unsigned HiReg = I->getOperand(2).getReg();
301 std::swap(LoReg, HiReg);
304 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
