| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| control_code2.s | 46 //CC = Dreg < Dreg (IU) ; /* less than, register, unsigned (a) */
47 CC = R7 < R0(IU);
48 CC = R6 < R0(IU);
49 CC = R7 < R1(IU);
50 CC = R1 < R7(IU);
51 CC = R0 < R6(IU);
53 //CC = Dreg < uimm3 (IU) ; /* less than, immediate, unsigned (a) */
54 CC = R7 < 0(IU);
55 CC = R6 < 0(IU);
56 CC = R7 < 7(IU);
[all...] |
| control_code2.d | 32 32: 87 09 CC = R7 < R0 \(IU\);
33 34: 86 09 CC = R6 < R0 \(IU\);
34 36: 8f 09 CC = R7 < R1 \(IU\);
35 38: b9 09 CC = R1 < R7 \(IU\);
36 3a: b0 09 CC = R0 < R6 \(IU\);
37 3c: 87 0d CC = R7 < 0x0 \(IU\);
38 3e: 86 0d CC = R6 < 0x0 \(IU\);
39 40: bf 0d CC = R7 < 0x7 \(IU\);
40 42: b9 0d CC = R1 < 0x7 \(IU\);
41 44: 07 0a CC = R7 <= R0 \(IU\);
[all...] |
| control_code.d | 14 e: be 09 CC = R6 < R7 \(IU\);
15 10: a7 0d CC = R7 < 0x4 \(IU\);
16 12: 1d 0a CC = R5 <= R3 \(IU\);
17 14: 2a 0e CC = R2 <= 0x5 \(IU\);
26 22: b5 09 CC = R5 < R6 \(IU\);
27 24: bf 0d CC = R7 < 0x7 \(IU\);
28 26: 08 0a CC = R0 <= R1 \(IU\);
29 28: 02 0e CC = R2 <= 0x0 \(IU\);
|
| invalid_arith_mode.s | 3 // All available modes: FU, IS, IU, T, TFU, S2RND, ISS2, IH, W32
22 R0 = R1.L * R2.H (IU);
30 A0 = R1.L * R2.H (IU);
|
| arith_mode.s | 8 R0.L = A0 (IU);
20 R0 = A0 (IU); // Not documented
29 R0.H = R1.L * R2.H (IU);
56 R0.L = (A0 = R1.L * R2.H) (IU);
68 R0 = (A0 = R1.L * R2.H) (IU); // Not documented
|
| arith_mode.d | 12 c: 83 c1 00 38 R0.L = A0 \(IU\);
21 30: 8b c1 00 38 R0 = A0 \(IU\);
27 48: 84 c3 0a 40 R0.H = R1.L \* R2.H \(IU\);
45 90: 83 c1 0a 22 R0.L = \(A0 = R1.L \* R2.H\) \(IU\);
54 b4: 8b c1 0a 22 R0 = \(A0 = R1.L \* R2.H\) \(IU\);
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| d10v-opc.c | 172 { "abs", SHORT_2, 1, IU, PAR|WF0, 0x5607, 0x7eff, { ADST } },
174 { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } },
175 { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } },
176 { "add2w", SHORT_2, 2, IU, PAR|WCAR, 0x1200, 0x7e23, { RDSTE, RSRCE } },
178 { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
179 { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
180 { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
181 { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
185 { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } },
189 { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } }
[all...] |
| d30v-opc.c | 267 { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
268 { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
269 { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
270 { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
273 { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
274 { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
275 { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
276 { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
277 { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
278 { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 }
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| bittest.l | 3 .*: Warning: Executing btst in IU in reverse serial may not work
4 .*: Warning: Executing bclr in IU may not work in parallel execution
5 .*: Warning: Executing bset in IU may not work
12 3 # Bit operation instructions \(BCLR, BNOT, BSET, BTST\) should not be placed in IU.
13 4 # If the user specifically indicates they should be in the IU, GAS will
15 6 # will fail in IU only occasionally. Thus GAS should pack them in MU for
28 .* Warning: Executing btst in IU in reverse serial may not work
31 .* Warning: Executing bclr in IU may not work in parallel execution
39 .* Warning: Executing bset in IU may not work
|
| mul.s | 1 # One of the rule on restricted sequence is consecutive IU instruction
2 # IU: MUL, MAC, MACS, MSUB, MSUBS (a)
3 # IU: MULHXpp, MULX2H, MUL2H (b)
5 # in IU in consecutive cycles in the order (a)->(b). It does neither prohibit
|
| bittest.s | 3 # Bit operation instructions (BCLR, BNOT, BSET, BTST) should not be placed in IU.
4 # If the user specifically indicates they should be in the IU, GAS will
6 # will fail in IU only occasionally. Thus GAS should pack them in MU for
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Analysis/ |
| IVUsers.h | 136 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
139 const SCEV *getExpr(const IVStrideUse &IU) const;
141 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
169 std::unique_ptr<IVUsers> IU;
176 IVUsers &getIU() { return *IU; }
177 const IVUsers &getIU() const { return *IU; }
|
| /external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/ |
| SimplifyIndVar.h | 53 bool simplifyIVUsers(IVUsers *IU, ScalarEvolution *SE, LPPassManager *LPM,
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-mips-elf/ |
| compressed-plt-1b.s | 1 # Define a function with all "uncompressed" (du and iu) references.
15 .if (\types) & IU
|
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| IVUsers.cpp | 228 const SCEV *IVUsers::getReplacementExpr(const IVStrideUse &IU) const {
229 return SE->getSCEV(IU.getOperandValToReplace());
233 const SCEV *IVUsers::getExpr(const IVStrideUse &IU) const {
235 TransformForPostIncUse(Normalize, getReplacementExpr(IU),
236 IU.getUser(), IU.getOperandValToReplace(),
237 const_cast<PostIncLoopSet &>(IU.getPostIncLoops()),
259 const SCEV *IVUsers::getStride(const IVStrideUse &IU, const Loop *L) const {
260 if (const SCEVAddRecExpr *AR = findAddRecForLoop(getExpr(IU), L))
|
| /external/llvm/lib/Analysis/ |
| IVUsers.cpp | 324 const SCEV *IVUsers::getReplacementExpr(const IVStrideUse &IU) const {
325 return SE->getSCEV(IU.getOperandValToReplace());
329 const SCEV *IVUsers::getExpr(const IVStrideUse &IU) const {
331 TransformForPostIncUse(Normalize, getReplacementExpr(IU),
332 IU.getUser(), IU.getOperandValToReplace(),
333 const_cast<PostIncLoopSet &>(IU.getPostIncLoops()),
355 const SCEV *IVUsers::getStride(const IVStrideUse &IU, const Loop *L) const {
356 if (const SCEVAddRecExpr *AR = findAddRecForLoop(getExpr(IU), L))
|
| /external/llvm/include/llvm/Analysis/ |
| IVUsers.h | 157 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
160 const SCEV *getExpr(const IVStrideUse &IU) const;
162 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
|
| /external/swiftshader/third_party/LLVM/include/llvm/Analysis/ |
| IVUsers.h | 154 const SCEV *getReplacementExpr(const IVStrideUse &IU) const;
157 const SCEV *getExpr(const IVStrideUse &IU) const;
159 const SCEV *getStride(const IVStrideUse &IU, const Loop *L) const;
|
