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  /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp 143 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
148 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
153 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
224 /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
745 /// '+/- imm8<<2' operand.
757 // {7-0} = imm8
758 int32_t Imm8 = MI.getOperand(OpIdx).getImm();
759 bool isAdd = Imm8 >= 0;
762 if (Imm8 < 0)
763 Imm8 = -Imm8
    [all...]
ARMAddressingModes.h 433 // addrmode3 := reg +/- imm8
485 // addrmode5 := reg +/- imm8*4
542 unsigned Imm8 = getNEONModImmVal(ModImm);
547 Val = Imm8;
552 Val = Imm8 << (8 * ByteNum);
557 Val = Imm8 << (8 * ByteNum);
562 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp 165 /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2'
171 /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2'
177 /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2'
253 /// getAddrMode5OpValue - Return encoding info for 'reg +/- (imm8 << 2)' operand.
258 /// getAddrMode5FP16OpValue - Return encoding info for 'reg +/- (imm8 << 1)' operand.
    [all...]
ARMAddressingModes.h 434 // addrmode3 := reg +/- imm8
486 // addrmode5 := reg +/- imm8*4
509 // addrmode5fp16 := reg +/- imm8*2
566 unsigned Imm8 = getNEONModImmVal(ModImm);
571 Val = Imm8;
576 Val = Imm8 << (8 * ByteNum);
581 Val = Imm8 << (8 * ByteNum);
586 Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
  /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 315 Imm8 = 1 << ImmShift,
408 /// storing a classifier in the imm8 field. To simplify our implementation,
430 case X86II::Imm8:
449 case X86II::Imm8:
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 404 Imm8 = 1 << ImmShift,
545 /// storing a classifier in the imm8 field. To simplify our implementation,
577 case X86II::Imm8:
597 case X86II::Imm8:
613 case X86II::Imm8:
  /external/swiftshader/third_party/subzero/src/
IceAssemblerARM32.cpp 220 IValueT &Cmode, IValueT &Imm8) {
225 Imm8 = Value;
274 // Value=rrrriiiiiiii where rrrr is the rotation, and iiiiiiii is the imm8
285 // Rn should be used, and iiiiiiiiiiii defines the rotated Imm8 value.
289 // Value=00000000pu0w0nnnn0000iiii0000jjjj where nnnn=Rn, iiiijjjj=Imm8, p=1
325 // Sets Encoding to a rotated Imm8 encoding of Value, if possible.
436 IValueT encodeImmRegOffsetEnc3(IValueT Rn, IOffsetT Imm8,
439 if (Imm8 < 0) {
440 Imm8 = -Imm8;
    [all...]
IceTargetLoweringARM32.cpp     [all...]
IceInstARM32.cpp 383 uint32_t Imm8 = Utils::rotateLeft32(Immediate, 2 * Rot);
384 if (Imm8 <= 0xFF) {
386 *Immed_8 = Imm8;
    [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
i386-opc.h 647 Imm8,
762 unsigned int imm8:1; member in struct:i386_operand_type::__anon116489
i386-gen.c 265 "Imm8" },
535 BITFIELD (Imm8),
    [all...]
  /external/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp     [all...]

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