| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 160 MachineInstr &LastInst = *I;
164 if (LastInst.getOpcode() == NVPTX::GOTO) {
165 TBB = LastInst.getOperand(0).getMBB();
167 } else if (LastInst.getOpcode() == NVPTX::CBranch) {
169 TBB = LastInst.getOperand(1).getMBB();
170 Cond.push_back(LastInst.getOperand(0));
186 LastInst.getOpcode() == NVPTX::GOTO) {
189 FBB = LastInst.getOperand(0).getMBB();
196 LastInst.getOpcode() == NVPTX::GOTO) {
198 I = LastInst;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 205 MachineInstr *LastInst = I;
209 if (IsBRU(LastInst->getOpcode())) {
210 TBB = LastInst->getOperand(0).getMBB();
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
221 TBB = LastInst->getOperand(1).getMBB();
223 Cond.push_back(LastInst->getOperand(0));
241 && IsBRU(LastInst->getOpcode())) {
247 FBB = LastInst->getOperand(0).getMBB();
254 IsBRU(LastInst->getOpcode())) {
256 I = LastInst;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeInstrInfo.cpp | 134 MachineInstr *LastInst = I;
137 unsigned LastOpc = LastInst->getOpcode();
140 TBB = LastInst->getOperand(0).getMBB();
145 TBB = LastInst->getOperand(1).getMBB();
146 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
147 Cond.push_back(LastInst->getOperand(0));
163 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
167 FBB = LastInst->getOperand(0).getMBB();
174 MBlaze::isUncondBranchOpcode(LastInst->getOpcode())) {
176 I = LastInst;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 231 MachineInstr *LastInst = I;
235 if (isUncondBranch(LastInst)) {
237 if (!LastInst->getOperand(0).isMBB())
239 TBB = LastInst->getOperand(0).getMBB();
241 } else if (isCondBranch(LastInst)) {
243 TBB = LastInst->getOperand(1).getMBB();
244 DEBUG(errs() << "Pushing LastInst: ");
245 DEBUG(LastInst->dump());
246 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
247 Cond.push_back(LastInst->getOperand(0))
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 204 MachineInstr *LastInst = I;
208 if (IsBRU(LastInst->getOpcode())) {
209 TBB = LastInst->getOperand(0).getMBB();
213 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
220 TBB = LastInst->getOperand(1).getMBB();
222 Cond.push_back(LastInst->getOperand(0));
239 && IsBRU(LastInst->getOpcode())) {
245 FBB = LastInst->getOperand(0).getMBB();
252 IsBRU(LastInst->getOpcode())) {
254 I = LastInst;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 236 MachineInstr *LastInst = I;
240 if (LastInst->getOpcode() == Alpha::BR) {
241 TBB = LastInst->getOperand(0).getMBB();
243 } else if (LastInst->getOpcode() == Alpha::COND_BRANCH_I ||
244 LastInst->getOpcode() == Alpha::COND_BRANCH_F) {
246 TBB = LastInst->getOperand(2).getMBB();
247 Cond.push_back(LastInst->getOperand(0));
248 Cond.push_back(LastInst->getOperand(1));
266 LastInst->getOpcode() == Alpha::BR) {
270 FBB = LastInst->getOperand(0).getMBB()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 197 MachineInstr *LastInst = &*I;
198 unsigned LastOpc = LastInst->getOpcode();
199 BranchInstrs.push_back(LastInst);
203 return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
221 if (LastInst->isUnconditionalBranch()) {
222 TBB = LastInst->getOperand(0).getMBB();
227 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
246 LastInst->eraseFromParent();
253 if (!LastInst->isUnconditionalBranch())
257 FBB = LastInst->getOperand(0).getMBB()
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 154 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
156 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm()));
157 Target = LastInst->getOperand(0).getMBB();
173 MachineInstr *LastInst = &*I;
174 unsigned LastOpc = LastInst->getOpcode();
179 TBB = LastInst->getOperand(0).getMBB();
184 parseCondBranch(LastInst, TBB, Cond);
198 LastInst->eraseFromParent();
199 LastInst = SecondLastInst;
200 LastOpc = LastInst->getOpcode()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 463 MachineInstr *LastInst = I;
467 if (LastInst->getOpcode() == PPC::B) {
468 if (!LastInst->getOperand(0).isMBB())
470 TBB = LastInst->getOperand(0).getMBB();
472 } else if (LastInst->getOpcode() == PPC::BCC) {
473 if (!LastInst->getOperand(2).isMBB())
476 TBB = LastInst->getOperand(2).getMBB();
477 Cond.push_back(LastInst->getOperand(0));
478 Cond.push_back(LastInst->getOperand(1));
480 } else if (LastInst->getOpcode() == PPC::BC)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 188 MachineInstr *LastInst = I;
192 if (LastInst->getOpcode() == PPC::B) {
193 if (!LastInst->getOperand(0).isMBB())
195 TBB = LastInst->getOperand(0).getMBB();
197 } else if (LastInst->getOpcode() == PPC::BCC) {
198 if (!LastInst->getOperand(2).isMBB())
201 TBB = LastInst->getOperand(2).getMBB();
202 Cond.push_back(LastInst->getOperand(0));
203 Cond.push_back(LastInst->getOperand(1));
220 LastInst->getOpcode() == PPC::B)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 193 MachineInstr *StartInst, *LastInst, *KillInst;
200 /// we cannot change LastInst's outgoing register.
203 /// The "color" of LastInst. This will be the preferred chain color,
209 : StartInst(MI), LastInst(MI), KillInst(nullptr),
218 LastInst = MI;
237 /// LastInst) is killed by MI with no intervening uses or defs.
250 MachineInstr *getLast() const { return LastInst; }
254 /// of the chain. This is the maximum of KillInst (if set) and LastInst.
256 return ++MachineBasicBlock::iterator(KillInst ? KillInst : LastInst);
297 LastInst->print(OS, /* SkipOpers= */true)
[all...] |
| AArch64InstrInfo.cpp | 64 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
67 switch (LastInst->getOpcode()) {
71 Target = LastInst->getOperand(1).getMBB();
72 Cond.push_back(LastInst->getOperand(0));
78 Target = LastInst->getOperand(1).getMBB();
80 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
81 Cond.push_back(LastInst->getOperand(0));
87 Target = LastInst->getOperand(2).getMBB();
89 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
90 Cond.push_back(LastInst->getOperand(0))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 294 MachineInstr *LastInst = &*I;
295 unsigned LastOpc = LastInst->getOpcode();
318 TBB = LastInst->getOperand(0).getMBB();
323 AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
340 LastInst->eraseFromParent();
350 FBB = LastInst->getOperand(0).getMBB();
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | 431 MachineInstr *LastInst = &*I;
435 if (&*I != LastInst && !I->isBundle() && isUnpredicatedTerminator(*I)) {
447 int LastOpcode = LastInst->getOpcode();
451 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB())
458 bool LastOpcodeHasNVJump = isNewValueJump(LastInst);
460 if (LastOpcodeHasJMP_c && !LastInst->getOperand(1).isMBB())
464 if (LastInst && !SecondLastInst) {
466 TBB = LastInst->getOperand(0).getMBB();
470 TBB = LastInst->getOperand(0).getMBB();
471 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 288 MachineInstr *LastInst = I;
291 unsigned LastOpc = LastInst->getOpcode();
294 TBB = LastInst->getOperand(0).getMBB();
299 TBB = LastInst->getOperand(0).getMBB();
300 Cond.push_back(LastInst->getOperand(1));
301 Cond.push_back(LastInst->getOperand(2));
315 LastInst->eraseFromParent();
316 LastInst = SecondLastInst;
317 LastOpc = LastInst->getOpcode();
320 TBB = LastInst->getOperand(0).getMBB()
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.cpp | 713 MachineInstr &LastInst = *I;
716 unsigned LastOpc = LastInst.getOpcode();
720 TBB = LastInst.getOperand(0).getMBB();
727 TBB = LastInst.getOperand(0).getMBB();
747 FBB = LastInst.getOperand(0).getMBB();
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceCfg.cpp | 685 auto &LastInst = Insts.back();
691 PreHeader->appendInst(&LastInst);
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
