| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/ |
| MmcHostDxe.c | 222 // Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
236 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
239 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
242 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
245 MmioOr32 (MMCHS_SYSCTL, CEN);
357 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
382 MmioOr32 (MMCHS_SYSCTL, SRC);
383 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
435 MmioWrite32 (MMCHS_SYSCTL, SRA);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
| MmcHostDxe.c | 222 // Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
236 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
239 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
242 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
245 MmioOr32 (MMCHS_SYSCTL, CEN);
357 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
382 MmioOr32 (MMCHS_SYSCTL, SRC);
383 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
435 MmioWrite32 (MMCHS_SYSCTL, SRA);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/ |
| MMCHS.c | 96 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
99 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
102 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
105 MmioOr32 (MMCHS_SYSCTL, CEN);
126 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
150 MmioOr32 (MMCHS_SYSCTL, SRC);
151 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
318 //Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
438 MmioOr32 (MMCHS_SYSCTL, SRC);
440 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/ |
| MMCHS.c | 96 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
99 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
102 while ((MmioRead32 (MMCHS_SYSCTL) & ICS_MASK) != ICS);
105 MmioOr32 (MMCHS_SYSCTL, CEN);
126 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
150 MmioOr32 (MMCHS_SYSCTL, SRC);
151 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
318 //Calculate Clock divider value to program in MMCHS_SYSCTL[CLKD] field.
438 MmioOr32 (MMCHS_SYSCTL, SRC);
440 while ((MmioRead32 (MMCHS_SYSCTL) & SRC));
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
| Omap3530MMCHS.h | 96 #define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530MMCHS.h | 96 #define MMCHS_SYSCTL (MMCHS1BASE + 0x12C)
|
