| /external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/ |
| MipsBaseInfo.h | 11 // the Mips target useful for the compiler back-end and the MC libraries.
27 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64:
28 case Mips::D0:
30 case Mips::AT: case Mips::AT_64: case Mips::F1: case Mips::D1_64
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsRegisterInfo.cpp | 1 //===- MipsRegisterInfo.cpp - MIPS Register Information -== -----*- C++ -*-===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
14 #define DEBUG_TYPE "mips-reg-info"
16 #include "Mips.h"
46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {}
49 /// Mips::RA, return the number that it corresponds to (e.g. 31).
54 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64
[all...] |
| MipsInstrInfo.cpp | 1 //===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
30 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
53 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) ||
54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) |
[all...] |
| MipsRelocations.h | 1 //===- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===//
10 // This file defines the Mips target-specific relocation types
21 namespace Mips{
|
| MipsFrameLowering.cpp | 1 //=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====//
10 // This file contains the Mips implementation of TargetFrameLowering class.
127 // FIXME: change this when mips goes MC".
128 BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
129 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
131 .addReg(Mips::AT);
132 NewReg = Mips::AT
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsABIInfo.cpp | 1 //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
22 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
23 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}
[all...] |
| MipsNaClELFStreamer.cpp | 1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
10 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
20 #include "Mips.h"
27 #define DEBUG_TYPE "mips-mc-nacl"
31 const unsigned IndirectBranchMaskReg = Mips::T6;
32 const unsigned LoadStoreStackMaskReg = Mips::T7;
51 if (MI.getOpcode() == Mips::JALR) {
55 return MI.getOperand(0).getReg() == Mips::ZERO;
57 return MI.getOpcode() == Mips::JR;
62 && MI.getOperand(0).getReg() == Mips::SP)
[all...] |
| MipsAsmBackend.cpp | 1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16
[all...] |
| MipsABIFlagsSection.h | 1 //===-- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -----*- C++ -*--===//
29 // The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
32 Mips::AFL_REG GPRSize;
34 Mips::AFL_REG CPR1Size;
36 Mips::AFL_REG CPR2Size;
38 Mips::AFL_EXT ISAExtension;
52 : Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
53 CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
54 ISAExtension(Mips::AFL_EXT_NONE), ASESet(0), OddSPReg(false)
[all...] |
| MipsABIFlagsSection.cpp | 1 //===-- MipsABIFlagsSection.cpp - Mips ELF ABI Flags Section ---*- C++ -*--===//
17 return Mips::Val_GNU_MIPS_ABI_FP_ANY;
19 return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
21 return Mips::Val_GNU_MIPS_ABI_FP_XX;
23 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
26 return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
27 : Mips::Val_GNU_MIPS_ABI_FP_64A;
28 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
49 return (uint8_t)Mips::AFL_REG_32;
|
| MipsMCCodeEmitter.cpp | 1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
69 case Mips::DSLL:
70 Inst.setOpcode(Mips::DSLL32);
72 case Mips::DSRL:
73 Inst.setOpcode(Mips::DSRL32);
75 case Mips::DSRA:
76 Inst.setOpcode(Mips::DSRA32);
78 case Mips::DROTR:
79 Inst.setOpcode(Mips::DROTR32);
81 case Mips::DSLL_MM64R6
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164))
[all...] |
| MipsRegisterInfo.cpp | 1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
15 #include "Mips.h"
40 #define DEBUG_TYPE "mips-reg-info"
45 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
47 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
57 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
59 return ABI.ArePtrs64bit() ? &Mips::GPRMM16_64RegClass
60 : &Mips::GPRMM16RegClass
[all...] |
| Mips16InstrInfo.cpp | 33 : MipsInstrInfo(STI, Mips::Bimm16), RI() {}
65 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
66 Mips::GPR32RegClass.contains(SrcReg))
67 Opc = Mips::MoveR3216;
68 else if (Mips::GPR32RegClass.contains(DestReg) &&
69 Mips::CPU16RegsRegClass.contains(SrcReg))
70 Opc = Mips::Move32R16;
71 else if ((SrcReg == Mips::HI0) &&
72 (Mips::CPU16RegsRegClass.contains(DestReg)))
73 Opc = Mips::Mfhi16, SrcReg = 0
[all...] |
| MipsInstrInfo.cpp | 1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
33 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
54 BuildMI(MBB, MI, DL, get(Mips::NOP));
129 "# of Mips branch conditions must be <= 3!");
174 "Invalid Mips branch condition!");
270 case Mips::BNE:
271 case Mips::BEQ:
279 case Mips::JR
[all...] |
| MipsOptionRecord.h | 11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
12 // specific ELF sections like .Mips.options. Specific records should subclass
15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID))
[all...] |
| MipsSERegisterInfo.cpp | 16 #include "Mips.h"
40 #define DEBUG_TYPE "mips-reg-info"
57 return &Mips::GPR32RegClass;
60 return &Mips::GPR64RegClass;
68 case Mips::LD_B:
69 case Mips::ST_B:
71 case Mips::LD_H:
72 case Mips::ST_H:
74 case Mips::LD_W:
75 case Mips::ST_W
[all...] |
| MipsLongBranch.cpp | 16 #include "Mips.h"
33 #define DEBUG_TYPE "mips-long-branch"
38 "skip-mips-long-branch",
40 cl::desc("MIPS: Skip long branch pass."),
44 "force-mips-long-branch",
46 cl::desc("MIPS: Expand all branches to long format."),
70 return "Mips Long Branch";
279 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP
[all...] |
| Mips16ISelLowering.cpp | 25 #define DEBUG_TYPE "mips-lower"
31 "pseudos for Mips 16"),
126 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
173 case Mips::SelBeqZ:
174 return emitSel16(Mips::BeqzRxImm16, MI, BB);
175 case Mips::SelBneZ:
176 return emitSel16(Mips::BnezRxImm16, MI, BB);
177 case Mips::SelTBteqZCmpi:
178 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB)
[all...] |
| MipsMachineFunction.cpp | 1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
24 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
43 ? &Mips::CPU16RegsRegClass
46 ? &Mips::GPRMM16_64RegClass
47 : &Mips::GPRMM16RegClass
51 ? &Mips::GPR64RegClass
52 : &Mips::GPR32RegClass;
60 ? &Mips::GPR64RegClass
61 : &Mips::GPR32RegClass;
73 const TargetRegisterClass *RC = &Mips::GPR32RegClass
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
10 // This class prints an Mips MCInst to a .s file.
37 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
84 case Mips::RDHWR:
85 case Mips::RDHWR64:
89 case Mips::Save16:
94 case Mips::SaveX16:
99 case Mips::Restore16:
104 case Mips::RestoreX16
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| dg.exp | 3 if { [llvm_supports_target Mips] } {
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
39 #define DEBUG_TYPE "mips-asm-parser"
94 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
95 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
96 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5
[all...] |
| /build/make/target/product/ |
| sdk_phone_mips.mk | 34 PRODUCT_MODEL := Android SDK for Mips
|
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 27 LLVM_TARGET(Mips)
|
