| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/SP804TimerDxe/ |
| SP804Timer.c | 156 MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, 0);
161 MmioAnd32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, 0);
166 MmioAnd32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, 0);
209 MmioAnd32 (SP804_TIMER_PERIODIC_BASE + SP804_TIMER_CONTROL_REG, ~SP804_TIMER_CTRL_ENABLE);
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| ExI.c | 101 MmioAnd32 ((UINTN) (GetPmcBase() + R_PCH_PMC_MTPMC1), ~((UINT32) BIT0+BIT1+BIT2)); //clear bit 0,1,2
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/ |
| UartInit.c | 188 MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
190 MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Library/BeagleBoardLib/ |
| BeagleBoard.c | 94 MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );
|
| /device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/ |
| BeagleBoard.c | 94 MmioAnd32 (CM_FCLKEN_PER, 0xFFFFFFFF ^ CM_ICLKEN_PER_EN_GPT3_ENABLE );
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/ |
| PL111Lcd.c | 125 MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.c | 148 MmioAnd32 (CM_FCLKEN_DSS, ~(EN_DSS1 | EN_DSS2 | EN_TV));
180 MmioAnd32 (DISPC_CONFIG, CLEARLOADMODE);
241 MmioAnd32 (GPIO6_BASE + GPIO_OE, ~BIT10);
|
| /device/linaro/bootloader/edk2/ArmPkg/Include/ |
| AsmMacroIoLib.h | 50 #define MmioAnd32(_Address, _AndData) \
170 #define MmioAnd32(Address, AndData) \
228 #define MmioAnd32(Address, AndData) MmioAnd32Macro Address, AndData
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/LcdGraphicsOutputDxe/ |
| LcdGraphicsOutputDxe.c | 148 MmioAnd32 (CM_FCLKEN_DSS, ~(EN_DSS1 | EN_DSS2 | EN_TV));
180 MmioAnd32 (DISPC_CONFIG, CLEARLOADMODE);
241 MmioAnd32 (GPIO6_BASE + GPIO_OE, ~BIT10);
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/OmapDmaLib/ |
| OmapDmaLib.c | 171 MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/Library/OmapDmaLib/ |
| OmapDmaLib.c | 171 MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchAccess.h | 86 MmioAnd32 ( \
194 MmioAnd32 ( \
297 MmioAnd32 ( \
391 #define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/MonoStatusCode/ |
| PlatformStatusCode.c | 356 MmioAnd32(IO_BASE_ADDRESS + 0x0520, (UINT32)~(0x00000187));
358 MmioAnd32(IO_BASE_ADDRESS + 0x0530, (UINT32)~(0x00000007));
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ |
| ArmVExpressSysConfig.c | 76 MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigRuntimeLib/ |
| ArmVExpressSysConfigRuntimeLib.c | 83 MmioAnd32(ARM_VE_SYS_CFGSTAT_REG, ~SYS_CFGSTAT_COMPLETE);
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/SP805WatchdogDxe/ |
| SP805Watchdog.c | 80 MmioAnd32(SP805_WDOG_CONTROL_REG, ~SP805_WDOG_CTRL_INTEN);
|
| /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/ |
| DebugCommunicationLibUsb.c | 291 MmioAnd32((UINTN)&DebugPortRegister->ControlStatus, (UINT32)~BIT4);
384 MmioAnd32((UINTN)&DebugPortRegister->ControlStatus, (UINT32)~0xF);
671 MmioAnd32((UINTN)PortStatus, (UINT32)~BIT8);
972 MmioAnd32((UINTN)&UsbDebugPortRegister->ControlStatus, (UINT32)~BIT4);
[all...] |
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
| PchInitPeim.c | 471 MmioAnd32 (IO_BASE_ADDRESS + 0x0520, ~(UINT32)0x07);
472 MmioAnd32 (IO_BASE_ADDRESS + 0x0530, ~(UINT32)0x07);
715 MmioAnd32 ((UINTN) (IoBase + 0x270), (UINT32) (~0x07));
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/ |
| MmcHostDxe.c | 236 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
483 MmioAnd32 (MMCHS_CON, ~INIT);
|
| /device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
| MmcHostDxe.c | 236 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
483 MmioAnd32 (MMCHS_CON, ~INIT);
|
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbHostDxe/ |
| DwUsbHostDxe.c | 289 MmioAnd32 (DwHc->DwUsbBase + HPRT0, ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
427 MmioAnd32 (DwHc->DwUsbBase + HPRT0, ~DWC2_HPRT0_PRTRST);
480 MmioAnd32 (DwHc->DwUsbBase + HPRT0, ~DWC2_HPRT0_PRTRST);
892 MmioAnd32 (DwHc->DwUsbBase + GOTGCTL, ~(DWC2_GOTGCTL_HSTSETHNPEN));
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/ |
| MMCHS.c | 96 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
409 MmioAnd32 (MMCHS_CON, ~INIT);
561 MmioAnd32 (MMCHS_CON, ~OD);
[all...] |
| /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/ |
| MMCHS.c | 96 MmioAnd32 (MMCHS_SYSCTL, ~CEN);
409 MmioAnd32 (MMCHS_CON, ~INIT);
561 MmioAnd32 (MMCHS_CON, ~OD);
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/PciEmulation/ |
| PciEmulation.c | 80 MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);
|
| /device/linaro/bootloader/edk2/ArmVirtPkg/Library/BaseCachingPciExpressLib/ |
| PciExpressLib.c | [all...] |
