/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ |
RTSMSec.c | 71 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
73 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformInitPei/ |
PlatformEarlyInit.c | 644 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));
645 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));
646 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));
647 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));
648 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));
649 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));
650 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));
651 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));
695 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));
700 MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01)); [all...] |
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Gpio/ |
Gpio.c | 78 MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
83 MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
88 MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
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/device/linaro/bootloader/edk2/Omap35xxPkg/Gpio/ |
Gpio.c | 78 MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_INPUT(Pin));
83 MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
88 MmioAndThenOr32(OutputEnableRegister, ~GPIO_OE_MASK(Pin), GPIO_OE_OUTPUT(Pin));
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/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ |
CTA9x4.c | 145 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
147 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
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/device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/ |
PlatformErratas.c | 91 MmioAndThenOr32 (
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/device/linaro/bootloader/edk2/ArmPkg/Include/ |
AsmMacroIoLib.h | 62 #define MmioAndThenOr32(_Address, _AndData, _OrData) \
177 #define MmioAndThenOr32(Address, AndData, OrData) \
233 #define MmioAndThenOr32(Address, AndData, OrData) MmioAndThenOr32Macro Address, AndData, OrData
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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
PchAccess.h | 96 MmioAndThenOr32 ( \
204 MmioAndThenOr32 ( \
307 MmioAndThenOr32 ( \
393 #define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/ |
UartInit.c | 179 MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
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/device/linaro/bootloader/OpenPlatformPkg/Drivers/Usb/DwUsbHostDxe/ |
DwUsbHostDxe.c | 204 MmioAndThenOr32 (DwHc->DwUsbBase + HCCHAR(DWC2_HC_CHANNEL), ~(DWC2_HCCHAR_MULTICNT_MASK | 282 MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0, 422 MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0, 475 MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0, 829 MmioAndThenOr32 (DwHc->DwUsbBase + HCFG, 903 MmioAndThenOr32 (DwHc->DwUsbBase + HCCHAR(i), 908 MmioAndThenOr32 (DwHc->DwUsbBase + HCCHAR(i), 1027 MmioAndThenOr32 (DwHc->DwUsbBase + HPRT0, [all...] |
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/ |
MmcHostDxe.c | 239 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
272 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
357 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
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/device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
MmcHostDxe.c | 239 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
272 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
357 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
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/device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV2/ |
ArmGicV2Dxe.c | 273 MmioAndThenOr32 (
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/device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV3/ |
ArmGicV3Dxe.c | 267 MmioAndThenOr32 (
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/MonoStatusCode/ |
PlatformStatusCode.c | 347 MmioAndThenOr32 (PMC_BASE_ADDRESS + R_PCH_PMC_GEN_PMCON_1, (UINT32) (~(B_PCH_PMC_GEN_PMCON_SUS_PWR_FLR + B_PCH_PMC_GEN_PMCON_PWROK_FLR)), BIT24);
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/ |
MMCHS.c | 99 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
126 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
367 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
[all...] |
/device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/ |
MMCHS.c | 99 MmioAndThenOr32 (MMCHS_SYSCTL, ~CLKD_MASK, NewCLKD << 6);
126 MmioAndThenOr32 (MMCHS_SYSCTL, ~DTO_MASK, DTO_VAL);
367 MmioAndThenOr32 (GPIO1_BASE + GPIO_OE, ~BIT23, BIT23);
[all...] |
/device/linaro/bootloader/edk2/ArmVirtPkg/Library/BaseCachingPciExpressLib/ |
PciExpressLib.c | [all...] |
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciExpressLib/ |
PciLib.c | [all...] |
/device/linaro/bootloader/edk2/MdePkg/Library/BasePciExpressLib/ |
PciExpressLib.c | [all...] |
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/ |
EdkIIGlueIoLib.h | [all...] |
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseIoLibIntrinsic/ |
IoHighLevel.c | [all...] |
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/DxeIoLibCpuIo/ |
IoHighLevel.c | [all...] |
/device/linaro/bootloader/edk2/IntelFrameworkPkg/Library/DxeIoLibCpuIo/ |
IoHighLevel.c | [all...] |
/device/linaro/bootloader/edk2/MdePkg/Include/Library/ |
IoLib.h | [all...] |