| /external/llvm/lib/Target/AMDGPU/ |
| SIMachineFunctionInfo.cpp | 34 TIDReg(AMDGPU::NoRegister),
35 ScratchRSrcReg(AMDGPU::NoRegister),
36 ScratchWaveOffsetReg(AMDGPU::NoRegister),
37 PrivateSegmentBufferUserSGPR(AMDGPU::NoRegister),
38 DispatchPtrUserSGPR(AMDGPU::NoRegister),
39 QueuePtrUserSGPR(AMDGPU::NoRegister),
40 KernargSegmentPtrUserSGPR(AMDGPU::NoRegister),
41 DispatchIDUserSGPR(AMDGPU::NoRegister),
42 FlatScratchInitUserSGPR(AMDGPU::NoRegister),
43 PrivateSegmentSizeUserSGPR(AMDGPU::NoRegister),
[all...] |
| AMDGPURegisterInfo.cpp | 28 static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
36 return AMDGPU::NoRegister;
|
| SIMachineFunctionInfo.h | 127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { }
129 bool hasReg() { return VGPR != AMDGPU::NoRegister;}
137 bool hasCalculatedTID() const { return TIDReg != AMDGPU::NoRegister; };
270 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
279 assert(Reg != AMDGPU::NoRegister && "Should never be unset");
|
| SIFrameLowering.cpp | 70 assert(ScratchRsrcReg != AMDGPU::NoRegister);
73 assert(ScratchWaveOffsetReg != AMDGPU::NoRegister);
78 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
|
| SIRegisterInfo.cpp | 183 if (ScratchWaveOffsetReg != AMDGPU::NoRegister) {
189 if (ScratchRSrcReg != AMDGPU::NoRegister) {
437 SOffset = AMDGPU::NoRegister;
444 if (SOffset == AMDGPU::NoRegister) {
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyReplacePhysRegs.cpp | 76 for (unsigned PReg = WebAssembly::NoRegister + 1;
84 unsigned VReg = WebAssembly::NoRegister;
88 if (VReg == WebAssembly::NoRegister)
|
| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 140 return Arm64ManagedRegister::NoRegister();
174 return ManagedRegister::NoRegister();
207 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
209 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
222 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
224 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
255 return ManagedRegister::NoRegister();
|
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 92 return MipsManagedRegister::NoRegister();
126 return ManagedRegister::NoRegister();
152 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
159 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
173 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
175 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
183 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
|
| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 130 return ArmManagedRegister::NoRegister();
140 return ArmManagedRegister::NoRegister();
156 return ArmManagedRegister::NoRegister();
185 return ManagedRegister::NoRegister();
229 entry_spills_.push_back(ManagedRegister::NoRegister(), 8);
240 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
259 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
261 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
269 entry_spills_.push_back(ManagedRegister::NoRegister(), 4);
|
| /art/compiler/jni/quick/x86/ |
| calling_convention_x86.cc | 62 return ManagedRegister::NoRegister(); // No free regs, so assembler uses push/pop
75 return ManagedRegister::NoRegister();
109 ManagedRegister res = ManagedRegister::NoRegister();
121 return ManagedRegister::NoRegister();
135 ManagedRegister res = ManagedRegister::NoRegister();
259 return ManagedRegister::NoRegister();
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 150 if (Reg != X86::NoRegister)
167 return X86::NoRegister;
172 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, Size);
301 : X86::NoRegister /* ScratchReg */);
422 : X86::NoRegister /* ScratchReg */);
505 if (FrameReg == X86::NoRegister)
534 assert(LocalFrameReg != X86::NoRegister);
538 if (MRI && FrameReg != X86::NoRegister) {
555 if (RegCtx.ScratchReg(32) != X86::NoRegister)
564 assert(LocalFrameReg != X86::NoRegister);
[all...] |
| /art/compiler/jni/quick/x86_64/ |
| calling_convention_x86_64.cc | 89 return ManagedRegister::NoRegister(); // No free regs, so assembler uses push/pop
98 return ManagedRegister::NoRegister();
132 ManagedRegister res = ManagedRegister::NoRegister();
239 ManagedRegister res = ManagedRegister::NoRegister();
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 115 return i != -1 && MI->getOperand(i).getReg() != PTX::NoRegister;
286 .addMBB(FBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
294 .addMBB(TBB).addReg(PTX::NoRegister).addImm(PTXPredicate::None);
321 SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
330 SDValue predReg = DAG->getRegister(PTX::NoRegister, MVT::i1);
338 MI->addOperand(MachineOperand::CreateReg(PTX::NoRegister, /*IsDef=*/false));
|
| PTXMachineFunctionInfo.h | 134 else if (Reg == PTX::NoRegister)
|
| PTXISelDAGToDAG.cpp | 133 SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
171 SDValue Pred = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
|
| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 77 return Mips64ManagedRegister::NoRegister();
111 return ManagedRegister::NoRegister();
|
| /art/compiler/utils/ |
| managed_register.h | 64 // It is valid to invoke Equals on and with a NoRegister.
73 static constexpr ManagedRegister NoRegister() {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.h | 58 s.Register = Hexagon::NoRegister;
64 void setError(unsigned e, unsigned r = Hexagon::NoRegister)
66 void setWarning(unsigned w, unsigned r = Hexagon::NoRegister)
|
| HexagonMCChecker.cpp | 31 HexagonMCChecker::Unconditional(Hexagon::NoRegister, false);
58 unsigned PredReg = Hexagon::NoRegister;
118 S = Hexagon::NoRegister;
|
| /art/compiler/utils/mips64/ |
| managed_register_mips64_test.cc | 24 TEST(Mips64ManagedRegister, NoRegister) {
25 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64();
202 ManagedRegister no_reg = ManagedRegister::NoRegister();
203 EXPECT_TRUE(no_reg.Equals(Mips64ManagedRegister::NoRegister()));
211 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::NoRegister()));
219 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::NoRegister()));
228 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::NoRegister()));
237 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::NoRegister()));
247 EXPECT_FALSE(reg_F31.Equals(Mips64ManagedRegister::NoRegister()));
257 EXPECT_FALSE(reg_W0.Equals(Mips64ManagedRegister::NoRegister()));
[all...] |
| /art/compiler/utils/arm/ |
| managed_register_arm_test.cc | 24 TEST(ArmManagedRegister, NoRegister) {
25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm();
290 ManagedRegister no_reg = ManagedRegister::NoRegister();
291 EXPECT_TRUE(no_reg.Equals(ArmManagedRegister::NoRegister()));
299 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::NoRegister()));
307 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::NoRegister()));
317 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::NoRegister()));
327 EXPECT_TRUE(!reg_S0.Equals(ArmManagedRegister::NoRegister()));
337 EXPECT_TRUE(!reg_S1.Equals(ArmManagedRegister::NoRegister()));
347 EXPECT_TRUE(!reg_S31.Equals(ArmManagedRegister::NoRegister()));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 268 return AArch64::NoRegister;
283 return findScratchNonCalleeSaveRegister(TmpMBB) != AArch64::NoRegister;
504 assert(scratchSPReg != AArch64::NoRegister);
[all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 25 TEST(Arm64ManagedRegister, NoRegister) {
26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64();
269 ManagedRegister no_reg = ManagedRegister::NoRegister();
270 EXPECT_TRUE(no_reg.Equals(Arm64ManagedRegister::NoRegister()));
279 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::NoRegister()));
287 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::NoRegister()));
297 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::NoRegister()));
303 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::NoRegister()));
313 EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::NoRegister()));
323 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::NoRegister()));
[all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 376 assert(Producer != Hexagon::NoRegister);
387 assert(Producer != Hexagon::NoRegister);
574 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister)
586 Hexagon::C1_0, Hexagon::NoRegister,
587 Hexagon::C3_2, Hexagon::NoRegister,
588 Hexagon::C7_6, Hexagon::NoRegister,
589 Hexagon::C9_8, Hexagon::NoRegister,
590 Hexagon::C11_10, Hexagon::NoRegister,
591 Hexagon::CS, Hexagon::NoRegister,
592 Hexagon::UPC, Hexagon::NoRegister
[all...] |
| /art/compiler/jni/quick/ |
| jni_compiler.cc | 361 ManagedRegister::NoRegister(), false);
408 ManagedRegister::NoRegister(), false);
483 ManagedRegister::NoRegister(), false);
614 ManagedRegister::NoRegister(), false);
[all...] |
