| /external/pcre/dist2/src/ |
| pcre2_jit_compile.c | 555 #define OP1(op, dst, dstw, src, srcw) \
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| h8300.h | 546 #define MOVFROM_REG_BW(CODE, NAME, SRC, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
547 {CODE, AV_H8, 4, NAME, {{SRC, RDIND, E}}, {{ 6, OP1, B31 | RDIND, SRC, E}}}, \
552 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, B30 | B20 | DISP2DST, 6, OP1, B31 | DSTDISPREG, SRC, E}}}, \
564 #define MOVTO_REG_BW(CODE, NAME, DST, PREFIX, OP1, OP2, OP3, OP4, RELAX16) \
565 {CODE, AV_H8, 4, NAME, {{RSIND, DST, E}}, {{ 6, OP1, B30 | RSIND, DST, E}}}, \
570 {CODE, AV_H8SX, 0, NAME, {{DISP2SRC, DST, E}}, {{PREFIX, B30 | B20 | DISP2SRC, 6, OP1, B30 | DISPREG, DST, E}}}, \
[all...] |
| tic6x-opcode-table.h | 42 #define OP1(a) 1, { a }
496 OP1(OLCST),
500 OP1(ORXREG1),
504 OP1(ORIRP1),
508 OP1(ORNRP1),
580 OP1(OLCST),
585 OP1(ORXREG1),
590 OP1(ORIRP1),
595 OP1(ORNRP1),
632 OP1(OLCST)
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| cr16-opc.c | 29 #define ARITH_BYTE_INST(NAME, OPC, OP1) \
33 {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \
38 #define ARITH1_BYTE_INST(NAME, OPC, OP1) \
40 {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
111 #define ARITH_INST32(NAME, OPC, OP1) \
113 {NAME, 3, OPC, 20, ARITH_INS, {{OP1,0}, {regp,16}}}
138 #define SHIFT_INST_A(NAME, OPC1, OPC2, SHIFT, OP1, OP2) \
140 {NAME, 1, OPC1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}}, \
142 {NAME, 1, OPC1+1, SHIFT, SHIFT_INS, {{OP1,20}, {OP2,16}}},\
150 #define SHIFT_INST_L(NAME, OPC1, OPC2, SHIFT, OP1, OP2)
[all...] |
| aarch64-tbl.h | 28 #define OP1(a) {OPND(a)}
55 /* e.g. SYS #<op1>, <Cn>, <Cm>, #<op2>{, <Xt>}. */
61 /* e.g. SYSL <Xt>, #<op1>, <Cn>, <Cm>, #<op2>. */
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600Defines.h | 41 OP1 = (1 << 10),
|
| R600InstrInfo.cpp | 134 return ((TargetFlags & R600_InstFlag::OP1) |
[all...] |
| /development/ndk/platforms/android-21/arch-arm64/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/r10/platforms/android-21/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/r10/platforms/android-23/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/r11/platforms/android-21/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/r11/platforms/android-23/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /prebuilts/ndk/r11/platforms/android-24/arch-arm64/usr/include/asm/ |
| kvm.h | 114 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /bionic/libc/kernel/uapi/asm-arm64/asm/ |
| kvm.h | 116 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) (KVM_REG_ARM64 | KVM_REG_ARM64_SYSREG | ARM64_SYS_REG_SHIFT_MASK(op0, OP0) | ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | ARM64_SYS_REG_SHIFT_MASK(crm, CRM) | ARM64_SYS_REG_SHIFT_MASK(op2, OP2))
|
| /external/kernel-headers/original/uapi/asm-arm64/asm/ |
| kvm.h | 184 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \
187 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 133 ((Desc.TSFlags & R600_InstFlag::OP1) ||
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_MCReconBlock_s.s | 298 LCLS OP1
301 OP1 SETS "AND"
304 OP1 SETS "ORR"
316 $OP1 $lsb0, $lsb0, $lsb1 ;// e0 = e0 & e1
|
| /external/boringssl/src/decrepit/cast/ |
| cast.c | 90 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \
93 t = (key[n * 2] OP1 R) & 0xffffffff; \
99 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \
|
| /external/valgrind/none/tests/amd64/ |
| fb_test_amd64.c | 449 #define OP1
454 #define OP1
459 #define OP1
464 #define OP1
690 void test_imulw2(int64 op0, int64 op1)
694 s1 = op1;
708 void test_imull2(int64 op0, int64 op1)
713 s1 = op1;
727 #define TEST_IMUL_IM(size, size1, op0, op1)\
738 : "r" (op1), "1" (flags), "0" (res));
[all...] |
| fb_test_amd64.h | 26 #ifdef OP1
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 658 SDValue OP1;
697 OP1 = Sext1;
709 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
720 OP0, OP1);
[all...] |
