| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| fd2_gmem.c | 67 OUT_RING(ring, CP_REG(REG_A2XX_RB_COLOR_INFO));
68 OUT_RING(ring, A2XX_RB_COLOR_INFO_SWAP(swap) |
73 OUT_RING(ring, CP_REG(REG_A2XX_RB_COPY_CONTROL));
74 OUT_RING(ring, 0x00000000); /* RB_COPY_CONTROL */
76 OUT_RING(ring, rsc->slices[0].pitch >> 5); /* RB_COPY_DEST_PITCH */
77 OUT_RING(ring, /* RB_COPY_DEST_INFO */
89 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
90 OUT_RING(ring, 3); /* VGT_MAX_VTX_INDX */
91 OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */
110 OUT_RING(ring, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET))
[all...] |
| fd2_draw.c | 52 OUT_RING(ring, CACHE_FLUSH);
93 OUT_RING(ring, CP_REG(REG_A2XX_VGT_INDX_OFFSET));
94 OUT_RING(ring, info->start);
97 OUT_RING(ring, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL));
98 OUT_RING(ring, 0x0000003b);
101 OUT_RING(ring, A2XX_TC_CNTL_STATUS_L2_INVALIDATE);
106 OUT_RING(ring, CP_REG(REG_A2XX_VGT_MAX_VTX_INDX));
107 OUT_RING(ring, info->max_index); /* VGT_MAX_VTX_INDX */
108 OUT_RING(ring, info->min_index); /* VGT_MIN_VTX_INDX */
114 OUT_RING(ring, CP_REG(REG_A2XX_UNKNOWN_2010))
[all...] |
| fd2_emit.c | 95 OUT_RING(ring, base);
97 OUT_RING(ring, *(dwords++));
110 OUT_RING(ring, start_base + (4 * (shader->first_immediate + i)));
111 OUT_RING(ring, shader->immediates[i].val[0]);
112 OUT_RING(ring, shader->immediates[i].val[1]);
113 OUT_RING(ring, shader->immediates[i].val[2]);
114 OUT_RING(ring, shader->immediates[i].val[3]);
140 OUT_RING(ring, 0x00010000 + (0x6 * const_idx));
142 OUT_RING(ring, sampler->tex0 | view->tex0);
144 OUT_RING(ring, view->tex2)
[all...] |
| fd2_program.c | 122 OUT_RING(ring, (so->type == SHADER_VERTEX) ? 0 : 1);
123 OUT_RING(ring, so->info.sizedwords);
125 OUT_RING(ring, so->bin[i]);
285 OUT_RING(ring, CP_REG(REG_A2XX_SQ_PROGRAM_CNTL));
286 OUT_RING(ring, A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(POSITION_2_VECTORS_SPRITE) |
|
| /external/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
| fd5_emit.c | 75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
84 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
86 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
90 OUT_RING(ring, dwords[i]);
104 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
108 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
110 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
120 OUT_RING(ring, 0xbad00000 | (i << 16));
121 OUT_RING(ring, 0xbad00000 | (i << 16));
126 OUT_RING(ring, 0xffffffff)
[all...] |
| fd5_gmem.c | 96 OUT_RING(ring, A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
101 OUT_RING(ring, A5XX_RB_MRT_PITCH(stride));
102 OUT_RING(ring, A5XX_RB_MRT_ARRAY_PITCH(size));
104 OUT_RING(ring, base); /* RB_MRT[i].BASE_LO */
105 OUT_RING(ring, 0x00000000); /* RB_MRT[i].BASE_HI */
112 OUT_RING(ring, A5XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
119 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
120 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
121 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_PITCH(0));
122 OUT_RING(ring, A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0))
[all...] |
| fd5_emit.h | 99 OUT_RING(ring, 0x00000000); /* UCHE_CACHE_INVALIDATE_MIN_LO */
100 OUT_RING(ring, 0x00000000); /* UCHE_CACHE_INVALIDATE_MIN_HI */
101 OUT_RING(ring, 0x00000000); /* UCHE_CACHE_INVALIDATE_MAX_LO */
102 OUT_RING(ring, 0x00000000); /* UCHE_CACHE_INVALIDATE_MAX_HI */
103 OUT_RING(ring, 0x00000012); /* UCHE_CACHE_INVALIDATE */
114 OUT_RING(ring, CP_SET_RENDER_MODE_0_MODE(mode));
115 OUT_RING(ring, 0x00000000); /* ADDR_LO */
116 OUT_RING(ring, 0x00000000); /* ADDR_HI */
117 OUT_RING(ring, COND(mode == GMEM, CP_SET_RENDER_MODE_3_GMEM_ENABLE));
118 OUT_RING(ring, 0x00000000)
[all...] |
| fd5_program.c | 112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
117 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
119 OUT_RING(ring, CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(0));
131 OUT_RING(ring, bin[i]);
229 OUT_RING(ring, REG_A5XX_VPC_SO_BUF_CNTL);
230 OUT_RING(ring, A5XX_VPC_SO_BUF_CNTL_ENABLE |
235 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(0));
236 OUT_RING(ring, ncomp[0]);
237 OUT_RING(ring, REG_A5XX_VPC_SO_NCOMP(1));
238 OUT_RING(ring, ncomp[1])
[all...] |
| fd5_draw.h | 64 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode));
66 OUT_RING(ring, instances); /* NumInstances */
67 OUT_RING(ring, count); /* NumIndices */
69 OUT_RING(ring, 0x0); /* XXX */
71 OUT_RING (ring, idx_size);
|
| fd5_draw.c | 56 OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
57 OUT_RING(ring, info->start_instance); /* ??? UNKNOWN_2209 */
60 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
176 OUT_RING(ring, FLUSH_SO_0 + i);
251 OUT_RING(ring, A5XX_RB_BLIT_CNTL_BUF(BLIT_MRT0 + i));
254 OUT_RING(ring, A5XX_RB_CLEAR_CNTL_FAST_CLEAR |
258 OUT_RING(ring, uc.ui[0]); /* RB_CLEAR_COLOR_DW0 */
259 OUT_RING(ring, uc.ui[1]); /* RB_CLEAR_COLOR_DW1 */
260 OUT_RING(ring, uc.ui[2]); /* RB_CLEAR_COLOR_DW2 */
261 OUT_RING(ring, uc.ui[3]); /* RB_CLEAR_COLOR_DW3 *
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
| fd4_emit.c | 77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
86 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
91 OUT_RING(ring, dwords[i]);
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/4) |
109 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
120 OUT_RING(ring, 0xbad00000 | (i << 16));
125 OUT_RING(ring, 0xffffffff);
152 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
156 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
163 OUT_RING(ring, sampler->texsamp0)
[all...] |
| fd4_gmem.c | 115 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
121 OUT_RING(ring, base);
122 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
129 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
172 OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
176 OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp));
177 OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
204 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
207 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
215 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 *
[all...] |
| fd4_query.c | 65 OUT_RING(ring, CP_REG(REG_A4XX_RB_SAMPLE_COUNT_CONTROL) | 0x80000000);
66 OUT_RING(ring, HW_QUERY_BASE_REG);
67 OUT_RING(ring, A4XX_RB_SAMPLE_COUNT_CONTROL_COPY |
71 OUT_RING(ring, DRAW4(DI_PT_POINTLIST_PSIZE, DI_SRC_SEL_AUTO_INDEX,
73 OUT_RING(ring, 1); /* NumInstances */
74 OUT_RING(ring, 0); /* NumIndices */
122 OUT_RING(ring, CP_ALWAYS_COUNT);
168 OUT_RING(ring, CP_REG_TO_MEM_0_REG(REG_A4XX_RBBM_PERFCTR_CP_0_LO) |
186 OUT_RING(ring, samp->offset);
190 OUT_RING(ring, CP_REG_TO_MEM_0_REG(HW_QUERY_BASE_REG)
[all...] |
| fd4_program.c | 113 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
118 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
131 OUT_RING(ring, bin[i]);
272 OUT_RING(ring, 0x00000003);
275 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
284 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
288 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
291 OUT_RING(ring, A4XX_HLSQ_CONTROL_3_REG_REGID(s[FS].v->pos_regid) |
293 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
296 OUT_RING(ring, A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen)
[all...] |
| fd4_draw.h | 75 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode));
77 OUT_RING(ring, instances); /* NumInstances */
78 OUT_RING(ring, count); /* NumIndices */
80 OUT_RING(ring, 0x0); /* XXX */
82 OUT_RING (ring, idx_size);
|
| fd4_draw.c | 58 OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
59 OUT_RING(ring, info->start_instance); /* ??? UNKNOWN_2209 */
62 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
173 OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
174 OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
175 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
183 OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
184 OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
185 OUT_RING(ring, 0);
|
| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| fd3_gmem.c | 112 OUT_RING(ring, A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
118 OUT_RING(ring, A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(base));
124 OUT_RING(ring, COND((i < nr_bufs) && bufs[i],
173 OUT_RING(ring, A3XX_RB_MODE_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
176 OUT_RING(ring, A3XX_RB_RENDER_CONTROL_BIN_WIDTH(32) |
181 OUT_RING(ring, A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
185 OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(128));
186 OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) |
193 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
201 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS)
[all...] |
| fd3_query.c | 58 OUT_RING(ring, CP_REG(REG_A3XX_RB_SAMPLE_COUNT_ADDR) | 0x80000000);
59 OUT_RING(ring, HW_QUERY_BASE_REG);
60 OUT_RING(ring, samp->offset);
63 OUT_RING(ring, A3XX_RB_SAMPLE_COUNT_CONTROL_COPY);
66 OUT_RING(ring, 0x00000000);
67 OUT_RING(ring, DRAW(DI_PT_POINTLIST_PSIZE, DI_SRC_SEL_AUTO_INDEX,
69 OUT_RING(ring, 0); /* NumIndices */
74 OUT_RING(ring, A3XX_RBBM_PERFCTR_CTL_ENABLE);
77 OUT_RING(ring, A3XX_VBIF_PERF_CNT_EN_CNT0 |
|
| fd3_emit.c | 77 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
86 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
91 OUT_RING(ring, dwords[i]);
105 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
109 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
120 OUT_RING(ring, 0xbad00000 | (i << 16));
125 OUT_RING(ring, 0xffffffff);
155 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
159 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
167 OUT_RING(ring, sampler->texsamp0)
[all...] |
| fd3_program.c | 128 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) |
133 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
140 OUT_RING(ring, bin[i]);
232 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
240 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
244 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31));
245 OUT_RING(ring, A3XX_HLSQ_CONTROL_3_REG_REGID(fp->pos_regid));
246 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
249 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
254 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode)
[all...] |
| fd3_emit.h | 101 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(0));
102 OUT_RING(ring, A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(0) |
|
| fd3_draw.c | 69 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
72 OUT_RING(ring, add_sat(info->min_index, info->index_bias)); /* VFD_INDEX_MIN */
73 OUT_RING(ring, add_sat(info->max_index, info->index_bias)); /* VFD_INDEX_MAX */
74 OUT_RING(ring, info->start_instance); /* VFD_INSTANCEID_OFFSET */
75 OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */
78 OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */
|
| /external/mesa3d/src/gallium/drivers/freedreno/ |
| freedreno_draw.h | 65 OUT_RING(ring, 0x00000000);
66 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX,
68 OUT_RING(ring, 0); /* NumIndices */
74 OUT_RING(ring, 0);
78 OUT_RING(ring, 0x00000000); /* viz query info. */
86 OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode, instances));
88 OUT_RING(ring, count); /* NumIndices */
91 OUT_RING (ring, idx_size);
|
| freedreno_util.h | 185 OUT_RING(struct fd_ringbuffer *ring, uint32_t data)
188 DBG("ring[%p]: OUT_RING %04x: %08x", ring,
194 /* like OUT_RING() but appends a cmdstream patch point to 'buf' */
270 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
278 OUT_RING(ring, CP_TYPE2_PKT);
286 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
310 OUT_RING(ring, CP_TYPE4_PKT | cnt |
320 OUT_RING(ring, CP_TYPE7_PKT | cnt |
330 OUT_RING(ring, 0x00000000);
359 OUT_RING(ring, dwords)
[all...] |
| freedreno_batch.h | 276 OUT_RING(ring, evt);
|
