/external/vixl/test/aarch32/ |
test-assembler-cond-rd-memop-immediate-512-a32.cc | [all...] |
test-assembler-cond-rd-memop-rs-a32.cc | [all...] |
test-assembler-cond-rd-memop-immediate-8192-a32.cc | [all...] |
test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | [all...] |
test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | [all...] |
test-simulator-cond-rd-memop-immediate-512-a32.cc | [all...] |
test-simulator-cond-rd-memop-immediate-8192-a32.cc | [all...] |
test-simulator-cond-rd-memop-rs-a32.cc | [all...] |
test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | [all...] |
test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | [all...] |
test-disasm-a32.cc | 676 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xfff123, PostIndex)), 680 COMPARE_A32(Ldr(r0, MemOperand(r1, 0xff123, PostIndex)), 683 COMPARE_A32(Ldr(r0, MemOperand(r1, -0xff123, PostIndex)), 687 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xfff12, PostIndex)), 691 COMPARE_T32(Ldr(r0, MemOperand(r1, 0xff12, PostIndex)), 694 COMPARE_T32(Ldr(r0, MemOperand(r1, -0xff12, PostIndex)), 724 MUST_FAIL_TEST_BOTH(Ldr(r0, MemOperand(r0, 0xfff12, PostIndex)), 760 COMPARE_T32(Ldr(r0, MemOperand(r1, minus, r2, PostIndex)), 774 COMPARE_A32(Ldr(pc, MemOperand(r0, r0, PostIndex)), "ldr pc, [r0], r0\n"); 775 COMPARE_T32(Ldr(pc, MemOperand(r0, r0, PostIndex)), [all...] |
/external/vixl/examples/aarch64/ |
add2-vectors.cc | 57 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); 59 __ St1(v0.V16B(), MemOperand(x0, 16, PostIndex)); 72 __ Ldrb(w6, MemOperand(x1, 1, PostIndex)); 74 __ Strb(w5, MemOperand(x0, 1, PostIndex));
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crc-checksums.cc | 57 __ Ldrb(w3, MemOperand(x2, 1, PostIndex));
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sum-array.cc | 49 __ Ldrb(w3, MemOperand(x2, 1, PostIndex)); // w3 = *(x2++)
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/external/vixl/test/aarch64/ |
test-trace-aarch64.cc | 169 __ ldp(w23, w24, MemOperand(x1, 8, PostIndex)); 172 __ ldp(x25, x26, MemOperand(x1, 16, PostIndex)); 175 __ ldpsw(x27, x28, MemOperand(x1, 8, PostIndex)); 178 __ ldr(w29, MemOperand(x1, 4, PostIndex)); 181 __ ldr(x2, MemOperand(x1, 8, PostIndex)); 184 __ ldrb(w3, MemOperand(x1, 1, PostIndex)); 187 __ ldrb(x4, MemOperand(x1, 1, PostIndex)); 190 __ ldrh(w5, MemOperand(x1, 2, PostIndex)); 193 __ ldrh(x6, MemOperand(x1, 2, PostIndex)); 196 __ ldrsb(w7, MemOperand(x1, 1, PostIndex)); [all...] |
test-disasm-aarch64.cc | [all...] |
test-assembler-aarch64.cc | 16797 int postindex = 2 * kXRegSizeInBytes; local [all...] |
/external/v8/src/arm/ |
codegen-arm.cc | 76 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); 80 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); 82 __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(dest, PostIndex)); 83 __ vst1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(dest, PostIndex)); 88 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); 89 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); 91 __ vst1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(dest, PostIndex)); 92 __ vst1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(dest, PostIndex)); 93 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex)); 94 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex)); [all...] |
macro-assembler-arm.h | 423 ldr(src2, MemOperand(sp, 4, PostIndex), cond); 424 ldr(src1, MemOperand(sp, 4, PostIndex), cond); 435 ldr(src3, MemOperand(sp, 4, PostIndex), cond); 440 ldr(src1, MemOperand(sp, 4, PostIndex), cond); 459 ldr(src4, MemOperand(sp, 4, PostIndex), cond); 468 ldr(src1, MemOperand(sp, 4, PostIndex), cond); [all...] |
/external/v8/src/regexp/arm64/ |
regexp-macro-assembler-arm64.cc | 255 __ Ldrb(w10, MemOperand(characters_address, 1, PostIndex)); 258 __ Ldrh(w10, MemOperand(characters_address, 2, PostIndex)); 336 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); 337 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); 488 __ Ldrb(w10, MemOperand(capture_start_address, 1, PostIndex)); 489 __ Ldrb(w11, MemOperand(current_position_address, 1, PostIndex)); 492 __ Ldrh(w10, MemOperand(capture_start_address, 2, PostIndex)); 493 __ Ldrh(w11, MemOperand(current_position_address, 2, PostIndex)); 894 MemOperand(output_array(), kPointerSize, PostIndex)); [all...] |
/external/v8/src/regexp/arm/ |
regexp-macro-assembler-arm.cc | 254 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); 255 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); 389 __ ldrb(r3, MemOperand(r0, char_size(), PostIndex)); 390 __ ldrb(r4, MemOperand(r2, char_size(), PostIndex)); 393 __ ldrh(r3, MemOperand(r0, char_size(), PostIndex)); 394 __ ldrh(r4, MemOperand(r2, char_size(), PostIndex)); 769 __ str(r2, MemOperand(r0, kPointerSize, PostIndex)); 770 __ str(r3, MemOperand(r0, kPointerSize, PostIndex)); [all...] |
/external/vixl/src/aarch32/ |
operands-aarch32.cc | 519 if (operand.GetAddrMode() == PostIndex) { 550 if (operand.GetAddrMode() == PostIndex) {
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/external/vixl/src/aarch64/ |
operands-aarch64.cc | 437 VIXL_ASSERT((addrmode == Offset) || (addrmode == PostIndex)); 481 bool MemOperand::IsPostIndex() const { return addrmode_ == PostIndex; }
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/art/compiler/optimizing/ |
intrinsics_arm64.cc | 185 __ Ldr(tmp_reg, MemOperand(src_curr_addr, element_size, PostIndex)); 212 __ Str(tmp_reg, MemOperand(dst_curr_addr, element_size, PostIndex)); [all...] |
intrinsics_arm_vixl.cc | 206 __ Ldr(tmp, MemOperand(src_curr_addr, element_size, PostIndex)); 233 __ Str(tmp, MemOperand(dst_curr_addr, element_size, PostIndex)); [all...] |