| /prebuilts/go/darwin-x86/src/runtime/ |
| memmove_s390x.s | 9 MOVD to+0(FP), R6
13 CMPBEQ R6, R4, done
23 MOVD R7, 0(R6)
24 MOVD R8, 8(R6)
28 CMPBGT R4, R6, forwards
30 CMPBLE R7, R6, forwards
31 ADD R5, R6, R8
47 MOVD R3, 0(R6)
49 MOVD R3, 8(R6)
51 ADD $16, R6
[all...] |
| memmove_mips64x.s | 21 ADDV R1, R3, R6 // end pointer
43 ADDV $-7, R6, R3 // R3 is end pointer-7
54 BEQ R1, R6, done
65 ADDV R1, R3, R6 // to-end pointer
68 SUBVU R6, R2, R4
77 AND $7, R6, R5
81 ADDV $-1, R6
82 MOVB R4, (R6)
89 SGTU R6, R3, R5
93 ADDV $-8, R6
[all...] |
| memclr_arm64.s | 12 // warnings from addpool when written as AND $7, R4, R6 (see
15 SUB R5, R4, R6 // R6 is N&7
27 CMP $0, R6
30 ADD R3, R6, R6
34 CMP R3, R6
|
| memmove_mipsx.s | 27 SGTU R1, R2, R6
28 BNE R6, backward
31 SGTU $4, R3, R6
32 BNE R6, f_small_copy
35 AND $3, R1, R6
36 BEQ R6, f_dest_aligned
37 SUBU R1, R0, R6
38 AND $3, R6
40 SUBU R6, R3
42 ADDU R6, R
[all...] |
| memclr_ppc64x.s | 17 SRAD $3, R4, R6 // R6: double words to clear
18 CMP R6, $0, CR1 // CR1[EQ] set if no double words
21 MOVD R6, CTR // R6 = number of double words
22 SRADCC $2, R6, R7 // 32 byte chunks?
46 RLDCLCC $61, R4, $3, R6 // remaining doublewords
48 MOVD R6, CTR // set up the CTR for doublewords
|
| /prebuilts/go/linux-x86/src/runtime/ |
| memmove_s390x.s | 9 MOVD to+0(FP), R6
13 CMPBEQ R6, R4, done
23 MOVD R7, 0(R6)
24 MOVD R8, 8(R6)
28 CMPBGT R4, R6, forwards
30 CMPBLE R7, R6, forwards
31 ADD R5, R6, R8
47 MOVD R3, 0(R6)
49 MOVD R3, 8(R6)
51 ADD $16, R6
[all...] |
| memmove_mips64x.s | 21 ADDV R1, R3, R6 // end pointer
43 ADDV $-7, R6, R3 // R3 is end pointer-7
54 BEQ R1, R6, done
65 ADDV R1, R3, R6 // to-end pointer
68 SUBVU R6, R2, R4
77 AND $7, R6, R5
81 ADDV $-1, R6
82 MOVB R4, (R6)
89 SGTU R6, R3, R5
93 ADDV $-8, R6
[all...] |
| memclr_arm64.s | 12 // warnings from addpool when written as AND $7, R4, R6 (see
15 SUB R5, R4, R6 // R6 is N&7
27 CMP $0, R6
30 ADD R3, R6, R6
34 CMP R3, R6
|
| memmove_mipsx.s | 27 SGTU R1, R2, R6
28 BNE R6, backward
31 SGTU $4, R3, R6
32 BNE R6, f_small_copy
35 AND $3, R1, R6
36 BEQ R6, f_dest_aligned
37 SUBU R1, R0, R6
38 AND $3, R6
40 SUBU R6, R3
42 ADDU R6, R
[all...] |
| memclr_ppc64x.s | 17 SRAD $3, R4, R6 // R6: double words to clear
18 CMP R6, $0, CR1 // CR1[EQ] set if no double words
21 MOVD R6, CTR // R6 = number of double words
22 SRADCC $2, R6, R7 // 32 byte chunks?
46 RLDCLCC $61, R4, $3, R6 // remaining doublewords
48 MOVD R6, CTR // set up the CTR for doublewords
|
| /prebuilts/go/darwin-x86/src/math/big/ |
| arith_ppc64le.s | 16 MOVD y+16(FP), R6
18 CMPU R4, R6
22 DIVDEU R6, R4, R3
23 DIVDU R6, R5, R7
24 MULLD R6, R3, R8
25 MULLD R6, R7, R20
31 CMPU R4, R6
37 SUB R6, R4, R4
|
| arith_arm.s | 23 MOVW.P 4(R3), R6
24 ADC.S R6, R5
48 MOVW.P 4(R3), R6
49 SBC.S R6, R5
139 MOVW.W -4(R2), R6
140 MOVW R6<<R3, R7
141 MOVW R6>>R4, R6
142 MOVW R6, c+28(FP)
146 MOVW.W -4(R2), R6
[all...] |
| /prebuilts/go/linux-x86/src/math/big/ |
| arith_ppc64le.s | 16 MOVD y+16(FP), R6
18 CMPU R4, R6
22 DIVDEU R6, R4, R3
23 DIVDU R6, R5, R7
24 MULLD R6, R3, R8
25 MULLD R6, R7, R20
31 CMPU R4, R6
37 SUB R6, R4, R4
|
| arith_arm.s | 23 MOVW.P 4(R3), R6
24 ADC.S R6, R5
48 MOVW.P 4(R3), R6
49 SBC.S R6, R5
139 MOVW.W -4(R2), R6
140 MOVW R6<<R3, R7
141 MOVW R6>>R4, R6
142 MOVW R6, c+28(FP)
146 MOVW.W -4(R2), R6
[all...] |
| /external/llvm/test/MC/Mips/ |
| macro-ddiv-bad.s | 2 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
4 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
8 # RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
12 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
18 # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
|
| macro-ddivu-bad.s | 2 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
4 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
6 # RUN: FileCheck %s --check-prefix=MIPS32-OR-R6
8 # RUN: FileCheck %s --check-prefix=MIPS64-NOT-R6
12 # MIPS32-OR-R6: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: division by zero
18 # MIPS64-NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
|
| macro-div-bad.s | 2 # RUN: FileCheck %s --check-prefix=R6
4 # RUN: FileCheck %s --check-prefix=R6
6 # RUN: FileCheck %s --check-prefix=NOT-R6
8 # RUN: FileCheck %s --check-prefix=NOT-R6
12 # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
15 # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
18 # NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
|
| macro-divu-bad.s | 2 # RUN: FileCheck %s --check-prefix=R6
4 # RUN: FileCheck %s --check-prefix=R6
6 # RUN: FileCheck %s --check-prefix=NOT-R6
8 # RUN: FileCheck %s --check-prefix=NOT-R6
12 # R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
15 # NOT-R6: :[[@LINE-1]]:3: warning: division by zero
18 # NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
|
| /prebuilts/go/darwin-x86/src/runtime/internal/atomic/ |
| asm_s390x.s | 95 ADD R5, R3, R6
96 CS R3, R6, (R4) // if R3==(R4) then (R4)=R6 else R3=(R4)
98 MOVW R6, ret+16(FP)
107 ADD R5, R3, R6
108 CSG R3, R6, (R4) // if R3==(R4) then (R4)=R6 else R3=(R4)
110 MOVD R6, ret+16(FP)
117 MOVW (R4), R6
119 CS R6, R3, (R4) // if R6==(R4) then (R4)=R3 else R6=(R4
[all...] |
| asm_ppc64x.s | 22 LWAR (R3), R6
23 CMPW R6, R4
49 LDAR (R3), R6
50 CMP R6, R4
175 // R6 = ((ptr & 3) * 8) = (ptr << 3) & (3*8)
176 RLDC $3, R3, $(3*8), R6
177 // Shift val for aligned ptr. R4 = val << R6
178 SLD R6, R4, R4
182 LWAR (R5), R6
183 OR R4, R6
[all...] |
| /prebuilts/go/linux-x86/src/runtime/internal/atomic/ |
| asm_s390x.s | 95 ADD R5, R3, R6
96 CS R3, R6, (R4) // if R3==(R4) then (R4)=R6 else R3=(R4)
98 MOVW R6, ret+16(FP)
107 ADD R5, R3, R6
108 CSG R3, R6, (R4) // if R3==(R4) then (R4)=R6 else R3=(R4)
110 MOVD R6, ret+16(FP)
117 MOVW (R4), R6
119 CS R6, R3, (R4) // if R6==(R4) then (R4)=R3 else R6=(R4
[all...] |
| asm_ppc64x.s | 22 LWAR (R3), R6
23 CMPW R6, R4
49 LDAR (R3), R6
50 CMP R6, R4
175 // R6 = ((ptr & 3) * 8) = (ptr << 3) & (3*8)
176 RLDC $3, R3, $(3*8), R6
177 // Shift val for aligned ptr. R4 = val << R6
178 SLD R6, R4, R4
182 LWAR (R5), R6
183 OR R4, R6
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| vector.d | 12 8: 09 c6 30 c0 R0 = VIT_MAX \(R0, R6\) \(ASR\);
23 24: 00 c4 06 8e R7 = R0 -\|\+ R6;
27 34: 00 c4 1c cc R6 = R3 -\|- R4;
28 38: 00 c4 2e de R7 = R5 -\|- R6 \(CO\);
30 40: 01 c4 1e c2 R0 = R3 \+\|\+ R6, R1 = R3 -\|- R6 \(ASL\);
31 44: 21 c4 ca 2d R7 = R1 \+\|- R2, R6 = R1 -\|\+ R2 \(S\);
33 4c: 04 c4 41 8d R5 = R0 \+ R1, R6 = R0 - R1 \(NS\);
36 58: 11 c4 [c-f][[:xdigit:]] 6c R3 = A0 \+ A1, R6 = A0 - A1 \(S\);
52 80: 06 c4 01 0c R6 = MAX \(R0, R1\) \(V\)
[all...] |
| /external/boringssl/src/ssl/test/runner/poly1305/ |
| sum_arm.s | 39 MOVM.IA (R7), [R2-R6]
44 AND R12, R6, R6
45 MOVM.IA.W [R2-R6], (R0)
50 EOR R6, R6, R6
51 MOVM.IA.W [R2-R6], (R0)
53 MOVM.IA [R2-R6], (R0)
84 EOR R6, R6, R
[all...] |
| /prebuilts/go/darwin-x86/src/vendor/golang_org/x/crypto/poly1305/ |
| sum_arm.s | 39 MOVM.IA (R7), [R2-R6]
44 AND R12, R6, R6
45 MOVM.IA.W [R2-R6], (R0)
50 EOR R6, R6, R6
51 MOVM.IA.W [R2-R6], (R0)
53 MOVM.IA [R2-R6], (R0)
84 EOR R6, R6, R
[all...] |
