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Searched
refs:RCId
(Results
1 - 18
of
18
) sorted by null
/external/llvm/lib/CodeGen/GlobalISel/
RegisterBank.cpp
28
for (unsigned
RCId
= 0, End = TRI.getNumRegClasses();
RCId
!= End; ++
RCId
) {
29
const TargetRegisterClass &RC = *TRI.getRegClass(
RCId
);
40
const TargetRegisterClass &SubRC = *TRI.getRegClass(
RCId
);
96
for (unsigned
RCId
= 0, End = TRI->getNumRegClasses();
RCId
!= End; ++
RCId
) {
97
const TargetRegisterClass &RC = *TRI->getRegClass(
RCId
);
RegisterBankInfo.cpp
67
void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned
RCId
,
78
else if (RB.covers(*TRI.getRegClass(
RCId
)))
86
WorkList.push_back(
RCId
);
87
Covered.set(
RCId
);
91
unsigned
RCId
= WorkList.pop_back_val();
93
const TargetRegisterClass &CurRC = *TRI.getRegClass(
RCId
);
149
if (SuperRCId ==
RCId
) {
/external/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/
ResourcePriorityQueue.h
113
int rawRegPressureDelta (SUnit *SU, unsigned
RCId
);
131
unsigned numberRCValPredInSU (SUnit *SU, unsigned
RCId
);
132
unsigned numberRCValSuccInSU (SUnit *SU, unsigned
RCId
);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
MachineLICM.cpp
231
unsigned &
RCId
, unsigned &RCCost) const;
670
unsigned &
RCId
, unsigned &RCCost) const {
674
RCId
= RC->getID();
677
RCId
= TLI->getRepRegClassFor(VT)->getID();
711
unsigned
RCId
, RCCost;
712
getRegisterClassIDAndCost(MI, Reg, i,
RCId
, RCCost);
714
RegPressure[
RCId
] += RCCost;
719
RegPressure[
RCId
] += RCCost;
721
RegPressure[
RCId
] -= RCCost;
746
unsigned
RCId
, RCCost
[
all
...]
/external/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp
70
ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned
RCId
) {
98
&& (TLI->getRegClassFor(VT)->getID() ==
RCId
)) {
108
unsigned
RCId
) {
136
&& (TLI->getRegClassFor(VT)->getID() ==
RCId
)) {
326
int ResourcePriorityQueue::rawRegPressureDelta(SUnit *SU, unsigned
RCId
) {
337
&& TLI->getRegClassFor(VT)->getID() ==
RCId
)
338
RegBalance += numberRCValSuccInSU(SU,
RCId
);
348
&& TLI->getRegClassFor(VT)->getID() ==
RCId
)
349
RegBalance -= numberRCValPredInSU(SU,
RCId
);
ScheduleDAGRRList.cpp
[
all
...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
ScheduleDAGRRList.cpp
[
all
...]
/external/llvm/lib/Target/NVPTX/InstPrinter/
NVPTXInstPrinter.cpp
38
unsigned
RCId
= (RegNo >> 28);
39
switch (
RCId
) {
/external/llvm/include/llvm/CodeGen/GlobalISel/
RegisterBankInfo.h
321
/// Add \p
RCId
to the set of register class that the register bank,
324
/// of \p
RCId
to the set of covered register classes.
336
/// \note This method does *not* add the super classes of \p
RCId
.
337
/// The rationale is if \p ID covers the registers of \p
RCId
, that
339
/// of
RCId
's superclasses.
345
void addRegBankCoverage(unsigned ID, unsigned
RCId
,
/external/clang/lib/Sema/
SemaExprObjC.cpp
[
all
...]
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