| /external/v8/src/x87/ |
| disasm-x87.cc | 18 REG_OPER_OP_ORDER,
33 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER},
34 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER},
35 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER},
36 {0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER},
37 {0x29, "sub", OPER_REG_OP_ORDER}, {0x2A, "subb", REG_OPER_OP_ORDER},
38 {0x2B, "sub", REG_OPER_OP_ORDER}, {0x31, "xor", OPER_REG_OP_ORDER},
39 {0x33, "xor", REG_OPER_OP_ORDER}, {0x38, "cmpb", OPER_REG_OP_ORDER},
40 {0x39, "cmp", OPER_REG_OP_ORDER}, {0x3A, "cmpb", REG_OPER_OP_ORDER},
[all...] |
| /external/v8/src/x64/ |
| disasm-x64.cc | 21 REG_OPER_OP_ORDER = 1, // Register destination, operand source.
25 BYTE_REG_OPER_OP_ORDER = REG_OPER_OP_ORDER | BYTE_SIZE_OPERAND_FLAG,
44 { 0x03, REG_OPER_OP_ORDER, "add" },
48 { 0x0B, REG_OPER_OP_ORDER, "or" },
52 { 0x13, REG_OPER_OP_ORDER, "adc" },
56 { 0x1B, REG_OPER_OP_ORDER, "sbb" },
60 { 0x23, REG_OPER_OP_ORDER, "and" },
64 { 0x2B, REG_OPER_OP_ORDER, "sub" },
68 { 0x33, REG_OPER_OP_ORDER, "xor" },
72 { 0x3B, REG_OPER_OP_ORDER, "cmp" }
[all...] |
| /external/v8/src/ia32/ |
| disasm-ia32.cc | 18 REG_OPER_OP_ORDER,
33 {0x01, "add", OPER_REG_OP_ORDER}, {0x03, "add", REG_OPER_OP_ORDER},
34 {0x09, "or", OPER_REG_OP_ORDER}, {0x0B, "or", REG_OPER_OP_ORDER},
35 {0x13, "adc", REG_OPER_OP_ORDER}, {0x1B, "sbb", REG_OPER_OP_ORDER},
36 {0x21, "and", OPER_REG_OP_ORDER}, {0x23, "and", REG_OPER_OP_ORDER},
37 {0x29, "sub", OPER_REG_OP_ORDER}, {0x2A, "subb", REG_OPER_OP_ORDER},
38 {0x2B, "sub", REG_OPER_OP_ORDER}, {0x31, "xor", OPER_REG_OP_ORDER},
39 {0x33, "xor", REG_OPER_OP_ORDER}, {0x38, "cmpb", OPER_REG_OP_ORDER},
40 {0x39, "cmp", OPER_REG_OP_ORDER}, {0x3A, "cmpb", REG_OPER_OP_ORDER},
[all...] |
