/external/vixl/test/aarch32/ |
test-assembler-cond-rd-operand-rn-ror-amount-t32.cc | 74 ShiftType ror; member in struct:vixl::aarch32::__anon38274::Operands 102 {{al, r0, r0, ROR, 0}, false, al, "al r0 r0 ROR 0", "al_r0_r0_ROR_0"}, 103 {{al, r0, r0, ROR, 8}, false, al, "al r0 r0 ROR 8", "al_r0_r0_ROR_8"}, 104 {{al, r0, r0, ROR, 16}, false, al, "al r0 r0 ROR 16", "al_r0_r0_ROR_16"}, 105 {{al, r0, r0, ROR, 24}, false, al, "al r0 r0 ROR 24", "al_r0_r0_ROR_24"}, 106 {{al, r0, r1, ROR, 0}, false, al, "al r0 r1 ROR 0", "al_r0_r1_ROR_0"} 1233 ShiftType ror = kTests[i].operands.ror; local [all...] |
test-assembler-cond-rd-operand-rn-ror-amount-a32.cc | 74 ShiftType ror; member in struct:vixl::aarch32::__anon38273::Operands 102 {{vc, r2, r5, ROR, 0}, false, al, "vc r2 r5 ROR 0", "vc_r2_r5_ROR_0"}, 103 {{eq, r5, r7, ROR, 0}, false, al, "eq r5 r7 ROR 0", "eq_r5_r7_ROR_0"}, 104 {{ge, r3, r2, ROR, 8}, false, al, "ge r3 r2 ROR 8", "ge_r3_r2_ROR_8"}, 105 {{cc, r11, r3, ROR, 16}, false, al, "cc r11 r3 ROR 16", "cc_r11_r3_ROR_16"}, 106 {{cs, r13, r6, ROR, 0}, false, al, "cs r13 r6 ROR 0", "cs_r13_r6_ROR_0"} 1345 ShiftType ror = kTests[i].operands.ror; local [all...] |
test-assembler-cond-rd-rn-operand-rm-ror-amount-a32.cc | 75 ShiftType ror; member in struct:vixl::aarch32::__anon38296::Operands 102 const TestData kTests[] = {{{ls, r3, r3, r13, ROR, 0}, 105 "ls r3 r3 r13 ROR 0", 107 {{cs, r2, r7, r1, ROR, 16}, 110 "cs r2 r7 r1 ROR 16", 112 {{mi, r13, r0, r2, ROR, 8}, 115 "mi r13 r0 r2 ROR 8", 117 {{lt, r0, r6, r1, ROR, 8}, 120 "lt r0 r6 r1 ROR 8", 122 {{al, r6, r4, r8, ROR, 16} 5135 ShiftType ror = kTests[i].operands.ror; local [all...] |
test-assembler-cond-rd-rn-operand-rm-ror-amount-t32.cc | 75 ShiftType ror; member in struct:vixl::aarch32::__anon38297::Operands 102 const TestData kTests[] = {{{al, r4, r0, r8, ROR, 16}, 105 "al r4 r0 r8 ROR 16", 107 {{al, r14, r13, r12, ROR, 24}, 110 "al r14 r13 r12 ROR 24", 112 {{al, r9, r10, r5, ROR, 16}, 115 "al r9 r10 r5 ROR 16", 117 {{al, r11, r13, r14, ROR, 8}, 120 "al r11 r13 r14 ROR 8", 122 {{al, r3, r12, r11, ROR, 16} 5135 ShiftType ror = kTests[i].operands.ror; local [all...] |
test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 121 {{al, r7, r8, r10, ROR, 21}, 124 "al r7 r8 r10 ROR 21", 126 {{al, r5, r5, r3, ROR, 12}, 129 "al r5 r5 r3 ROR 12", 136 {{al, r9, r10, r11, ROR, 2}, 139 "al r9 r10 r11 ROR 2", 151 {{al, r2, r11, r1, ROR, 9}, 154 "al r2 r11 r1 ROR 9", 161 {{al, r6, r13, r3, ROR, 1}, 164 "al r6 r13 r3 ROR 1" [all...] |
test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 136 {{cc, r10, r5, r1, ROR, 10}, 139 "cc r10 r5 r1 ROR 10", 141 {{ge, r3, r14, r7, ROR, 7}, 144 "ge r3 r14 r7 ROR 7", 171 {{cs, r12, r3, r0, ROR, 20}, 174 "cs r12 r3 r0 ROR 20", 176 {{vs, r1, r6, r9, ROR, 14}, 179 "vs r1 r6 r9 ROR 14", 186 {{vc, r14, r13, r10, ROR, 7}, 189 "vc r14 r13 r10 ROR 7" [all...] |
test-assembler-cond-rd-operand-rn-shift-amount-1to31-a32.cc | 104 {{vc, r5, r5, ROR, 10}, false, al, "vc r5 r5 ROR 10", "vc_r5_r5_ROR_10"}, 105 {{ne, r3, r4, ROR, 17}, false, al, "ne r3 r4 ROR 17", "ne_r3_r4_ROR_17"}, 106 {{cs, r9, r10, ROR, 16}, false, al, "cs r9 r10 ROR 16", "cs_r9_r10_ROR_16"}, 107 {{lt, r0, r2, ROR, 29}, false, al, "lt r0 r2 ROR 29", "lt_r0_r2_ROR_29"}, 108 {{al, r11, r2, ROR, 23}, false, al, "al r11 r2 ROR 23", "al_r11_r2_ROR_23"} [all...] |
test-assembler-cond-rd-operand-rn-shift-amount-1to31-t32.cc | 104 {{al, r14, r8, ROR, 21}, false, al, "al r14 r8 ROR 21", "al_r14_r8_ROR_21"}, 105 {{al, r5, r13, ROR, 4}, false, al, "al r5 r13 ROR 4", "al_r5_r13_ROR_4"}, 106 {{al, r0, r3, ROR, 4}, false, al, "al r0 r3 ROR 4", "al_r0_r3_ROR_4"}, 107 {{al, r3, r14, ROR, 7}, false, al, "al r3 r14 ROR 7", "al_r3_r14_ROR_7"}, 111 {{al, r0, r9, ROR, 17}, false, al, "al r0 r9 ROR 17", "al_r0_r9_ROR_17"} [all...] |
test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 602 {{al, r0, r2, plus, r14, ROR, 9, Offset}, 605 "al r0 r2 plus r14 ROR 9 Offset", 617 {{al, r0, r4, plus, r12, ROR, 13, Offset}, 620 "al r0 r4 plus r12 ROR 13 Offset", 627 {{al, r0, r7, plus, r0, ROR, 25, Offset}, 630 "al r0 r7 plus r0 ROR 25 Offset", 647 {{al, r0, r7, plus, r12, ROR, 11, Offset}, 650 "al r0 r7 plus r12 ROR 11 Offset", [all...] |
test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 350 {{al, r4, r12, plus, r9, ROR, 12, Offset}, 351 "al r4 r12 plus r9 ROR 12 Offset", 380 {{al, r0, r11, plus, r4, ROR, 2, Offset}, 381 "al r0 r11 plus r4 ROR 2 Offset", 390 {{al, r2, r11, plus, r9, ROR, 29, Offset}, 391 "al r2 r11 plus r9 ROR 29 Offset", 410 {{al, r5, r1, plus, r3, ROR, 19, Offset}, 411 "al r5 r1 plus r3 ROR 19 Offset", 430 {{al, r7, r14, plus, r0, ROR, 17, Offset}, 431 "al r7 r14 plus r0 ROR 17 Offset" [all...] |
test-assembler-cond-rd-operand-rn-shift-rs-a32.cc | 110 {{ge, r11, r13, ROR, r2}, 113 "ge r11 r13 ROR r2", 121 {{eq, r3, r0, ROR, r11}, false, al, "eq r3 r0 ROR r11", "eq_r3_r0_ROR_r11"}, 127 {{ge, r14, r6, ROR, r13}, 130 "ge r14 r6 ROR r13", 138 {{ge, r4, r6, ROR, r7}, false, al, "ge r4 r6 ROR r7", "ge_r4_r6_ROR_r7"}, 160 {{hi, r9, r11, ROR, r13}, 163 "hi r9 r11 ROR r13" [all...] |
test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 111 {{al, r12, r3, ROR, r5}, false, al, "al r12 r3 ROR r5", "al_r12_r3_ROR_r5"}, 133 {{al, r12, r11, ROR, r7}, 136 "al r12 r11 ROR r7", 143 {{al, r11, r7, ROR, r0}, false, al, "al r11 r7 ROR r0", "al_r11_r7_ROR_r0"}, 144 {{al, r6, r13, ROR, r2}, false, al, "al r6 r13 ROR r2", "al_r6_r13_ROR_r2"}, 155 {{al, r4, r2, ROR, r3}, false, al, "al r4 r2 ROR r3", "al_r4_r2_ROR_r3"} [all...] |
test-assembler-cond-rd-operand-rn-shift-rs-t32-narrow-out-it-block.cc | 120 {{al, r0, r0, ROR, r0}, false, al, "al r0 r0 ROR r0", "al_r0_r0_ROR_r0"}, 121 {{al, r0, r0, ROR, r1}, false, al, "al r0 r0 ROR r1", "al_r0_r0_ROR_r1"}, 122 {{al, r0, r0, ROR, r2}, false, al, "al r0 r0 ROR r2", "al_r0_r0_ROR_r2"}, 123 {{al, r0, r0, ROR, r3}, false, al, "al r0 r0 ROR r3", "al_r0_r0_ROR_r3"}, 124 {{al, r0, r0, ROR, r4}, false, al, "al r0 r0 ROR r4", "al_r0_r0_ROR_r4"} [all...] |
test-assembler-cond-rd-operand-rn-shift-rs-t32-in-it-block.cc | 99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"}, 100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"}, 104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"}, 116 {{eq, r5, r5, ROR, r2}, true, eq, "eq r5 r5 ROR r2", "eq_r5_r5_ROR_r2"}, 122 {{ge, r6, r6, ROR, r3}, true, ge, "ge r6 r6 ROR r3", "ge_r6_r6_ROR_r3"} [all...] |
test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 126 {{vs, r11, r0, r14, ROR, r1}, 129 "vs r11 r0 r14 ROR r1", 131 {{vc, r5, r0, r11, ROR, r4}, 134 "vc r5 r0 r11 ROR r4", 186 {{hi, r6, r3, r0, ROR, r4}, 189 "hi r6 r3 r0 ROR r4", 216 {{ne, r4, r10, r9, ROR, r5}, 219 "ne r4 r10 r9 ROR r5", 226 {{pl, r1, r0, r1, ROR, r1}, 229 "pl r1 r0 r1 ROR r1" [all...] |
test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | 141 ShiftType ror; member in struct:vixl::aarch32::__anon38338::Operands 450 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0}, 451 "eq r0 r0 ROR 0", 455 {{ne, r0, r0, ROR, 0}, 456 "ne r0 r0 ROR 0", 460 {{cs, r0, r0, ROR, 0}, 461 "cs r0 r0 ROR 0", 465 {{cc, r0, r0, ROR, 0}, 466 "cc r0 r0 ROR 0", 470 {{mi, r0, r0, ROR, 0} 726 ShiftType ror = kTests[i].operands.ror; local [all...] |
test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | 141 ShiftType ror; member in struct:vixl::aarch32::__anon38339::Operands 450 const TestLoopData kTests[] = {{{eq, r0, r0, ROR, 0}, 451 "eq r0 r0 ROR 0", 455 {{ne, r0, r0, ROR, 0}, 456 "ne r0 r0 ROR 0", 460 {{cs, r0, r0, ROR, 0}, 461 "cs r0 r0 ROR 0", 465 {{cc, r0, r0, ROR, 0}, 466 "cc r0 r0 ROR 0", 470 {{mi, r0, r0, ROR, 0} 726 ShiftType ror = kTests[i].operands.ror; local [all...] |
/frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
h264bsd_interpolate_ver_half.s | 173 UXTB16 tmpa, tmp3, ROR #8 ;// |g4|g2| 174 UXTAB16 tmpa, tmpa, tmp4, ROR #8 ;// |g4+m4|g2+m2| 178 UXTB16 tmpb, tmp2, ROR #8 ;// |c4|c2| 180 UXTAB16 tmpb, tmpb, tmp5, ROR #8 ;// |c4+r4|c2+r2| 181 UXTAB16 tmpa, tmpa, tmp1, ROR #8 ;// 16+20(G+M)+A 182 UXTAB16 tmpa, tmpa, tmp6, ROR #8 ;// 16+20(G+M)+A+T 217 UXTB16 tmpa, tmp4, ROR #8 ;// |g4|g2| 218 UXTAB16 tmpa, tmpa, tmp5, ROR #8 ;// |g4+m4|g2+m2| 222 UXTB16 tmpb, tmp3, ROR #8 ;// |c4|c2| 224 UXTAB16 tmpb, tmpb, tmp6, ROR #8 ;// |c4+r4|c2+r2 [all...] |
h264bsd_interpolate_ver_quarter.s | 174 UXTB16 tmpa, tmp3, ROR #8 ;// |g4|g2| 175 UXTAB16 tmpa, tmpa, tmp4, ROR #8 ;// |g4+m4|g2+m2| 179 UXTB16 tmpb, tmp2, ROR #8 ;// |c4|c2| 181 UXTAB16 tmpb, tmpb, tmp5, ROR #8 ;// |c4+r4|c2+r2| 182 UXTAB16 tmpa, tmpa, tmp1, ROR #8 ;// 16+20(G+M)+A 183 UXTAB16 tmpa, tmpa, tmp6, ROR #8 ;// 16+20(G+M)+A+T 226 UXTB16 tmpa, tmp4, ROR #8 ;// |g4|g2| 227 UXTAB16 tmpa, tmpa, tmp5, ROR #8 ;// |g4+m4|g2+m2| 231 UXTB16 tmpb, tmp3, ROR #8 ;// |c4|c2| 233 UXTAB16 tmpb, tmpb, tmp6, ROR #8 ;// |c4+r4|c2+r2 [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
addthumb2err.s | 12 add sp, sp, r0, ROR #3 17 adds sp, sp, r0, ROR #3 22 sub sp, sp, r0, ROR #3 27 subs sp, sp, r0, ROR #3
|
archv6.s | 51 sxtah r2, r4, r5, ROR #8 53 sxtahne r2, r4, r5, ROR #8 57 sxtab16 r2, r4, r5, ROR #8 59 sxtab16ne r2, r4, r5, ROR #8 61 sxtab r2, r4, r5, ROR #8 63 sxtabne r2, r4, r5, ROR #8 134 sxth r2, r5, ROR #8 136 sxthne r2, r5, ROR #8 138 sxtb16 r2, r5, ROR #8 140 sxtb16ne r2, r5, ROR # [all...] |
/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 121 UXTAB16 Temp1, ValC, ValD, ROR #8 122 UXTAB16 Temp3, ValE, ValB, ROR #8 124 UXTAB16 Acc0, ValA, ValF, ROR #8 130 UXTAB16 Temp1, ValE, ValD, ROR #8 131 UXTAB16 Temp3, ValC, ValF, ROR #8 135 UXTAB16 Acc1, ValG, ValB, ROR #8 139 UXTAB16 Acc2, ValC, ValH, ROR #8 148 UXTAB16 Temp1, ValG, ValD, ROR #8 149 UXTAB16 Acc3, ValI, ValD, ROR #8 150 UXTAB16 Temp2, ValE, ValF, ROR # [all...] |
armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 124 UXTAB16 ValC1, r0x00ff00ff, ValC, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] 127 UXTAB16 ValE1, r0x00ff00ff, ValE, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] 129 UXTAB16 ValCD1, ValC1, ValD, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 d3 0 d1] 134 UXTAB16 ValEB1, ValE1, ValB, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 b3 0 b1] 138 UXTAB16 ValED1, ValE1, ValD, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 d3 0 d1] 144 UXTAB16 ValCF1, ValC1, ValF, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 f3 0 f1] 154 UXTAB16 ValA1, r0x00ff00ff, ValA, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255] 156 UXTAB16 ValAF1, ValA1, ValF, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255] + [0 f3 0 f1] 166 UXTAB16 ValG1, r0x00ff00ff, ValG, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255] 168 UXTAB16 ValGB1, ValG1, ValB, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255] + [0 b3 0 b1] [all...] |
armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 145 UXTAB16 Temp1, ValC, ValD, ROR #8 146 UXTAB16 Temp3, ValE, ValB, ROR #8 148 UXTAB16 Acc0, ValA, ValF, ROR #8 154 UXTAB16 Temp1, ValE, ValD, ROR #8 155 UXTAB16 Temp3, ValC, ValF, ROR #8 159 UXTAB16 Acc1, ValG, ValB, ROR #8 162 UXTAB16 Acc2, ValC, ValH, ROR #8 167 UXTAB16 Temp1, ValG, ValD, ROR #8 168 UXTAB16 Acc3, ValI, ValD, ROR #8 169 UXTAB16 Temp2, ValE, ValF, ROR # [all...] |
armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 152 UXTAB16 ValC1, r0x00ff00ff, ValC, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] 155 UXTAB16 ValE1, r0x00ff00ff, ValE, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] 157 UXTAB16 ValCD1, ValC1, ValD, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 d3 0 d1] 162 UXTAB16 ValEB1, ValE1, ValB, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 b3 0 b1] 166 UXTAB16 ValED1, ValE1, ValD, ROR #8 ;// [0 e3 0 e1] + [0 255 0 255] + [0 d3 0 d1] 171 UXTAB16 ValCF1, ValC1, ValF, ROR #8 ;// [0 c3 0 c1] + [0 255 0 255] + [0 f3 0 f1] 181 UXTAB16 ValA1, r0x00ff00ff, ValA, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255] 183 UXTAB16 ValAF1, ValA1, ValF, ROR #8 ;// [0 a3 0 a1] + [0 255 0 255] + [0 f3 0 f1] 191 UXTAB16 ValG1, r0x00ff00ff, ValG, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255] 193 UXTAB16 ValGB1, ValG1, ValB, ROR #8 ;// [0 g3 0 g1] + [0 255 0 255] + [0 b3 0 b1] [all...] |