| /external/vogar/src/vogar/tasks/ |
| RmTask.java | 21 import vogar.commands.Rm;
24 private final Rm rm; field in class:RmTask
27 public RmTask(Rm rm, File file) {
28 super("rm " + file);
29 this.rm = rm;
34 rm.file(file);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| mul-overlap.l | 2 [^:]*:5: Rd and Rm should be different in mul
3 [^:]*:6: Rd and Rm should be different in mla
4 [^:]*:8: rdhi, rdlo and rm must all be different
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 81 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift) = 0;
82 virtual uint32_t reg_rrx(int Rm) = 0;
83 virtual uint32_t reg_reg(int Rm, int type, int Rs) = 0;
87 // (immediate and Rm can be negative, which indicates U=0)
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0) = 0;
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0) = 0;
94 // (immediate and Rm can be negative, which indicates U=0)
97 virtual uint32_t reg_pre(int Rm, int W=0) = 0;
98 virtual uint32_t reg_post(int Rm) = 0;
129 int Rd, int Rm, int Rs, int Rn) = 0
[all...] |
| ARMAssembler.cpp | 215 int Rd, int Rm, int Rs, int Rn) {
216 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
217 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn);
219 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm;
222 int Rd, int Rm, int Rs) {
223 if (Rd == Rm) { int t = Rm; Rm=Rs; Rs=t; }
[all...] |
| ARMAssemblerProxy.cpp | 93 uint32_t ARMAssemblerProxy::reg_imm(int Rm, int type, uint32_t shift)
95 return mTarget->reg_imm(Rm, type, shift);
98 uint32_t ARMAssemblerProxy::reg_rrx(int Rm)
100 return mTarget->reg_rrx(Rm);
103 uint32_t ARMAssemblerProxy::reg_reg(int Rm, int type, int Rs)
105 return mTarget->reg_reg(Rm, type, Rs);
111 // (immediate and Rm can be negative, which indicates U=0)
122 uint32_t ARMAssemblerProxy::reg_scale_pre(int Rm, int type, uint32_t shift, int W)
124 return mTarget->reg_scale_pre(Rm, type, shift, W);
127 uint32_t ARMAssemblerProxy::reg_scale_post(int Rm, int type, uint32_t shift
[all...] |
| ARMAssembler.h | 70 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
71 virtual uint32_t reg_rrx(int Rm);
72 virtual uint32_t reg_reg(int Rm, int type, int Rs);
76 // (immediate and Rm can be negative, which indicates U=0)
79 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
80 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
83 // (immediate and Rm can be negative, which indicates U=0)
86 virtual uint32_t reg_pre(int Rm, int W=0);
87 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| ARMAssemblerProxy.h | 59 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
60 virtual uint32_t reg_rrx(int Rm);
61 virtual uint32_t reg_reg(int Rm, int type, int Rs);
65 // (immediate and Rm can be negative, which indicates U=0)
68 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
69 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
72 // (immediate and Rm can be negative, which indicates U=0)
75 virtual uint32_t reg_pre(int Rm, int W=0);
76 virtual uint32_t reg_post(int Rm);
83 int Rd, int Rm, int Rs, int Rn)
[all...] |
| Arm64Assembler.h | 83 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
84 virtual uint32_t reg_rrx(int Rm);
85 virtual uint32_t reg_reg(int Rm, int type, int Rs);
90 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
91 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
94 virtual uint32_t reg_pre(int Rm, int W=0);
95 virtual uint32_t reg_post(int Rm);
102 int Rd, int Rm, int Rs, int Rn);
104 int Rd, int Rm, int Rs);
106 int RdLo, int RdHi, int Rm, int Rs)
[all...] |
| Arm64Assembler.cpp | 375 uint32_t Rm;
381 Rm = mAddrMode.reg_imm_Rm;
387 Rm = Op2;
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
471 int Rm = mAddrMode.reg_imm_Rm;
473 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount)
[all...] |
| MIPS64Assembler.h | 73 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
74 virtual uint32_t reg_rrx(int Rm);
75 virtual uint32_t reg_reg(int Rm, int type, int Rs);
79 // (immediate and Rm can be negative, which indicates U=0)
82 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
83 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
86 // (immediate and Rm can be negative, which indicates U=0)
89 virtual uint32_t reg_pre(int Rm, int W=0);
90 virtual uint32_t reg_post(int Rm);
99 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPSAssembler.h | 68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift);
69 virtual uint32_t reg_rrx(int Rm);
70 virtual uint32_t reg_reg(int Rm, int type, int Rs);
74 // (immediate and Rm can be negative, which indicates U=0)
77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0);
78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0);
81 // (immediate and Rm can be negative, which indicates U=0)
84 virtual uint32_t reg_pre(int Rm, int W=0);
85 virtual uint32_t reg_post(int Rm);
94 int Rd, int Rm, int Rs, int Rn)
[all...] |
| MIPS64Assembler.cpp | 220 uint32_t ArmToMips64Assembler::reg_imm(int Rm, int type, uint32_t shift)
222 amode.reg = Rm;
228 uint32_t ArmToMips64Assembler::reg_rrx(int Rm)
234 uint32_t ArmToMips64Assembler::reg_reg(int Rm, int type, int Rs)
242 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
263 uint32_t ArmToMips64Assembler::reg_scale_pre(int Rm, int type,
268 amode.reg = Rm;
275 uint32_t ArmToMips64Assembler::reg_scale_post(int Rm, int type, uint32_t shift)
281 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
301 uint32_t ArmToMips64Assembler::reg_pre(int Rm, int W
[all...] |
| MIPSAssembler.cpp | 229 uint32_t ArmToMipsAssembler::reg_imm(int Rm, int type, uint32_t shift)
231 amode.reg = Rm;
237 uint32_t ArmToMipsAssembler::reg_rrx(int Rm)
243 uint32_t ArmToMipsAssembler::reg_reg(int Rm, int type, int Rs)
251 // LDR(B)/STR(B)/PLD (immediate and Rm can be negative, which indicate U=0)
272 uint32_t ArmToMipsAssembler::reg_scale_pre(int Rm, int type,
277 amode.reg = Rm;
284 uint32_t ArmToMipsAssembler::reg_scale_post(int Rm, int type, uint32_t shift)
290 // LDRH/LDRSB/LDRSH/STRH (immediate and Rm can be negative, which indicate U=0)
314 uint32_t ArmToMipsAssembler::reg_pre(int Rm, int W
[all...] |
| /external/vogar/src/vogar/commands/ |
| Rm.java | 23 * A rm command.
25 public final class Rm {
28 public Rm(Log log) {
33 new Command(log, "rm", "-rf", file.getPath()).execute();
|
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /external/vogar/test/vogar/android/ |
| AbstractModeTest.java | 37 import vogar.commands.Rm;
52 protected Rm rm; field in class:AbstractModeTest
70 rm = new Rm(console);
85 run = new Run(vogar, false, console, mkdir, androidSdk, new Rm(console), target,
|
| /external/vogar/src/vogar/ |
| LocalTarget.java | 26 import vogar.commands.Rm;
39 private final Rm rm; field in class:LocalTarget
41 public LocalTarget(Log log, Mkdir mkdir, Rm rm) {
43 this.rm = rm;
62 @Override public void rm(File file) { method in class:LocalTarget
63 rm.file(file);
|
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| decode.go | 232 Rm := Reg(x & (1<<4 - 1))
236 return Rm
238 return RegShift{Rm, typ, count}
241 Rm := Reg(x & (1<<4 - 1))
244 return RegShiftReg{Rm, typ, Rs}
247 Rm := Reg(x & (1<<4 - 1))
250 return Rm
252 return RegShift{Rm, typ, count}
417 // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| decode.go | 232 Rm := Reg(x & (1<<4 - 1))
236 return Rm
238 return RegShift{Rm, typ, count}
241 Rm := Reg(x & (1<<4 - 1))
244 return RegShiftReg{Rm, typ, Rs}
247 Rm := Reg(x & (1<<4 - 1))
250 return Rm
252 return RegShift{Rm, typ, count}
417 // Treat [<Rn>],+/-<Rm> like [<Rn>,+/-<Rm>{,<shift>}]{!
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ArmDisassembler.c | 171 UINT32 Rn, Rd, Rm;
186 Rm = (OpCode & 0xf);
201 // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
236 // A5.2.3 [<Rn>, +/-<Rm>]
237 // A5.2.6 [<Rn>, +/-<Rm>]!
240 // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
241 // A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
254 AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, RRX]%a", gReg[Rn], SIGN (U), gReg[Rm], WRITE (W));
260 AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (U), gReg[Rm], Type, shift_imm, WRITE (W));
267 // A5.2.9 [<Rn>], +/-<Rm>
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellLevel2CommandsLib/ |
| UefiShellLevel2CommandsLib.inf | 44 Rm.c
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
