| /external/vixl/src/aarch64/ |
| operands-aarch64.cc | 321 // Extend modes SXTX and UXTX require a 64-bit register.
322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
335 ((extend_ == UXTX) || (extend_ == SXTX) ||
401 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
403 // SXTX extend mode requires a 64-bit offset register.
404 VIXL_ASSERT(regoffset.Is64Bits() || (extend != SXTX));
462 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
463 VIXL_ASSERT((regoffset_.Is64Bits() || (extend_ != SXTX)));
|
| disasm-aarch64.cc | 165 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext"
168 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext";
[all...] |
| macro-assembler-aarch64.cc | 855 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
[all...] |
| constants-aarch64.h | 292 SXTX = 7
[all...] |
| simulator-aarch64.cc | 416 case SXTX:
[all...] |
| assembler-aarch64.cc | [all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| addsub.s | 29 // or implicitly UXTX, SXTX or LSL; otherwise it Wm.
32 .ifnc \extend, SXTX
102 .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 48 SXTX,
67 case AArch64_AM::SXTX: return "sxtx";
134 case 7: return AArch64_AM::SXTX;
150 /// 111 ==> sxtx
161 case AArch64_AM::SXTX: return 7; break;
197 /// 111 ==> sxtx
|
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 351 // Extend modes SXTX and UXTX require a 64-bit register.
352 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX));
468 // SXTX extend mode requires a 64-bit offset register.
469 DCHECK(regoffset.Is64Bits() || (extend != SXTX));
519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
520 DCHECK((regoffset_.Is64Bits() || (extend_ != SXTX)));
[all...] |
| disasm-arm64.cc | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
[all...] |
| constants-arm64.h | 346 SXTX = 7
[all...] |
| simulator-arm64.cc | [all...] |
| macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
[all...] |
| assembler-arm64.cc | [all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 367 SXTX
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 991 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
999 // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
1001 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
1007 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
1016 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) &&
[all...] |
| /external/vixl/test/aarch64/ |
| test-disasm-aarch64.cc | 434 COMPARE(adds(x27, x28, Operand(x29, SXTX)), "adds x27, x28, x29, sxtx");
460 COMPARE(subs(x27, x28, Operand(x29, SXTX)), "subs x27, x28, x29, sxtx");
[all...] |
| test-assembler-aarch64.cc | 642 __ Orr(x13, x0, Operand(x1, SXTX, 3));
736 __ Orn(x13, x0, Operand(x1, SXTX, 3));
803 __ And(x13, x0, Operand(x1, SXTX, 3));
941 __ Bic(x13, x0, Operand(x1, SXTX, 3));
1065 __ Eor(x13, x0, Operand(x1, SXTX, 3));
1132 __ Eon(x13, x0, Operand(x1, SXTX, 3));
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | 596 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
[all...] |
