| /art/compiler/optimizing/ |
| intrinsics_mips.cc | 455 __ Seleqz(TMP, TMP, in_hi);
508 __ Seleqz(out, in_hi, in_lo);
552 __ Seleqz(TMP, TMP, in_lo);
[all...] |
| intrinsics_mips64.cc | 674 // MOVF, MOVT, and MOVZ). The SELEQZ and SELNEZ instructions always
679 // needs to use a pair of SELEQZ/SELNEZ instructions. After
682 // output registers from the SELEQZ/SELNEZ instructions to get the
697 __ Seleqz(out, lhs, AT);
701 __ Seleqz(AT, rhs, AT);
706 __ Seleqz(out, rhs, AT);
710 __ Seleqz(AT, lhs, AT);
[all...] |
| code_generator_mips.cc | [all...] |
| /art/compiler/utils/mips/ |
| assembler_mips32r6_test.cc | 374 TEST_F(AssemblerMIPS32r6Test, Seleqz) {
375 DriverStr(RepeatRRR(&mips::MipsAssembler::Seleqz, "seleqz ${reg1}, ${reg2}, ${reg3}"), "seleqz");
403 DriverStr(RepeatFFF(&mips::MipsAssembler::SeleqzS, "seleqz.s ${reg1}, ${reg2}, ${reg3}"),
404 "seleqz.s");
408 DriverStr(RepeatFFF(&mips::MipsAssembler::SeleqzD, "seleqz.d ${reg1}, ${reg2}, ${reg3}"),
409 "seleqz.d");
[all...] |
| assembler_mips.h | 248 void Seleqz(Register rd, Register rs, Register rt); // R6
[all...] |
| assembler_mips.cc | 664 void MipsAssembler::Seleqz(Register rd, Register rs, Register rt) {
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | [all...] |
| assembler_mips64.h | 536 void Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt);
[all...] |
| assembler_mips64.cc | 657 void Mips64Assembler::Seleqz(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
[all...] |
