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Searched
refs:Src1Reg
(Results
1 - 10
of
10
) sorted by null
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCCompound.cpp
84
unsigned DstReg, SrcReg,
Src1Reg
, Src2Reg;
101
Src1Reg
= MI.getOperand(1).getReg();
104
HexagonMCInstrInfo::isIntRegForSubInst(
Src1Reg
) &&
146
Src1Reg
= MI.getOperand(1).getReg();
148
HexagonMCInstrInfo::isIntRegForSubInst(
Src1Reg
) &&
160
Src1Reg
= MI.getOperand(0).getReg();
161
if (Hexagon::P0 ==
Src1Reg
|| Hexagon::P1 ==
Src1Reg
)
HexagonMCDuplexInfo.cpp
178
unsigned DstReg, PredReg, SrcReg,
Src1Reg
, Src2Reg;
317
Src1Reg
= MCI.getOperand(0).getReg();
319
if (HexagonMCInstrInfo::isIntReg(
Src1Reg
) &&
321
Hexagon::R29 ==
Src1Reg
&& inRange<5, 2>(MCI, 1)) {
325
if (HexagonMCInstrInfo::isIntRegForSubInst(
Src1Reg
) &&
333
Src1Reg
= MCI.getOperand(0).getReg();
335
if (HexagonMCInstrInfo::isIntRegForSubInst(
Src1Reg
) &&
352
Src1Reg
= MCI.getOperand(0).getReg();
354
if (HexagonMCInstrInfo::isIntRegForSubInst(
Src1Reg
) &&
362
Src1Reg
= MCI.getOperand(0).getReg()
[
all
...]
/external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp
[
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...]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
MLxExpansionPass.cpp
212
unsigned
Src1Reg
= MI->getOperand(2).getReg();
226
.addReg(
Src1Reg
, getKillRegState(Src1Kill))
/external/llvm/lib/Target/ARM/
MLxExpansionPass.cpp
278
unsigned
Src1Reg
= MI->getOperand(2).getReg();
294
.addReg(
Src1Reg
, getKillRegState(Src1Kill))
/external/llvm/lib/Target/AMDGPU/
R600InstrInfo.h
270
unsigned
Src1Reg
= 0) const;
R600InstrInfo.cpp
[
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...]
SIInstrInfo.cpp
[
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...]
/external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp
[
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...]
/external/llvm/lib/Target/Mips/
MipsFastISel.cpp
994
unsigned
Src1Reg
= getRegForValue(SI->getTrueValue());
998
if (!
Src1Reg
|| !Src2Reg || !CondReg)
1016
.addReg(
Src1Reg
).addReg(ZExtCondReg).addReg(TempReg);
[
all
...]
Completed in 137 milliseconds