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    Searched refs:Src2Reg (Results 1 - 7 of 7) sorted by null

  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCDuplexInfo.cpp 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
318 Src2Reg = MCI.getOperand(2).getReg();
320 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
326 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
334 Src2Reg = MCI.getOperand(2).getReg();
336 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
353 Src2Reg = MCI.getOperand(2).getReg();
355 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg) &&
363 Src2Reg = MCI.getOperand(2).getReg();
364 if (HexagonMCInstrInfo::isDblRegForSubInst(Src2Reg) &
    [all...]
HexagonMCCompound.cpp 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
102 Src2Reg = MI.getOperand(2).getReg();
105 HexagonMCInstrInfo::isIntRegForSubInst(Src2Reg))
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
MLxExpansionPass.cpp 213 unsigned Src2Reg = MI->getOperand(3).getReg();
227 .addReg(Src2Reg, getKillRegState(Src2Kill));
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp     [all...]
  /external/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 279 unsigned Src2Reg = MI->getOperand(3).getReg();
295 .addReg(Src2Reg, getKillRegState(Src2Kill));
  /external/llvm/lib/Target/AArch64/
AArch64FastISel.cpp     [all...]
  /external/llvm/lib/Target/Mips/
MipsFastISel.cpp 995 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
998 if (!Src1Reg || !Src2Reg || !CondReg)
1014 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
    [all...]

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