| /external/llvm/lib/Linker/ |
| IRMover.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRDFOpt.cpp | 123 const MachineOperand &SrcOp = MI->getOperand(1);
125 { SrcOp.getReg(), SrcOp.getSubReg() });
|
| HexagonFrameLowering.cpp | [all...] |
| HexagonExpandCondsets.cpp | 249 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
607 /// Generate a conditional transfer, copying the value SrcOp to the
611 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
615 MachineInstr *MI = SrcOp.getParent();
625 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
630 .addOperand(SrcOp);
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenInstruction.cpp | 237 std::pair<unsigned,unsigned> SrcOp =
239 if (SrcOp > DestOp)
243 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp);
|
| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.cpp | 244 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false);
245 if (SrcOp > DestOp) {
246 std::swap(SrcOp, DestOp);
250 unsigned FlatOpNo = Ops.getFlattenedOperandNumber(SrcOp);
|
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/tools/llvm-c-test/ |
| echo.cpp | 429 LLVMValueRef SrcOp = LLVMGetOperand(Src, 0);
430 LLVMBasicBlockRef SrcBB = LLVMValueAsBasicBlock(SrcOp);
|
| /external/llvm/lib/Analysis/ |
| InstructionSimplify.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 861 const MachineOperand &SrcOp = MI.getOperand(1);
863 assert(!SrcOp.isFPImm());
864 if (SrcOp.isImm()) {
865 APInt Imm(64, SrcOp.getImm());
873 assert(SrcOp.isReg());
875 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
878 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.h | 791 SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | [all...] |
| /prebuilts/tools/common/m2/repository/com/tunnelvisionlabs/antlr4/4.5/ |
| antlr4-4.5.jar | |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 133 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineScheduler.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceTargetLoweringX86BaseImpl.h | [all...] |
| IceTargetLoweringARM32.cpp | [all...] |
| IceTargetLoweringMIPS32.cpp | [all...] |
| /prebuilts/checkstyle/ |
| checkstyle.jar | |
| /prebuilts/tools/common/m2/repository/org/antlr/antlr4/4.5.3/ |
| antlr4-4.5.3.jar | |
| /prebuilts/tools/common/offline-m2/org/antlr/antlr4/4.5.3/ |
| antlr4-4.5.3.jar | |
