| /external/pcre/dist2/src/sljit/ |
| sljitNativePPC_32.c | 100 SLJIT_ASSERT(src2 == TMP_REG2);
105 SLJIT_ASSERT(src2 == TMP_REG2);
109 SLJIT_ASSERT(src2 == TMP_REG2);
132 SLJIT_ASSERT(src2 == TMP_REG2);
136 SLJIT_ASSERT(src2 == TMP_REG2);
166 SLJIT_ASSERT(src2 == TMP_REG2);
173 SLJIT_ASSERT(src2 == TMP_REG2);
177 SLJIT_ASSERT(src2 == TMP_REG2);
184 SLJIT_ASSERT(src2 == TMP_REG2);
188 SLJIT_ASSERT(src2 == TMP_REG2);
[all...] |
| sljitNativePPC_64.c | 126 FAIL_IF(push_inst(compiler, EXTSW | S(src2) | A(TMP_REG2))); \
127 src2 = TMP_REG2; \
137 FAIL_IF(push_inst(compiler, EXTSW | S(src2) | A(TMP_REG2))); \
138 src2 = TMP_REG2; \
219 SLJIT_ASSERT(src2 == TMP_REG2);
224 SLJIT_ASSERT(src2 == TMP_REG2);
228 SLJIT_ASSERT(src2 == TMP_REG2);
254 SLJIT_ASSERT(src2 == TMP_REG2);
258 SLJIT_ASSERT(src2 == TMP_REG2);
290 SLJIT_ASSERT(src2 == TMP_REG2);
[all...] |
| sljitNativePPC_common.c | 95 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
102 #define TMP_CALL_REG TMP_REG2
[all...] |
| sljitNativeSPARC_common.c | 89 /* TMP_REG2 is not used by getput_arg */
91 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
642 arg2 goes to TMP_REG2, imm or src reg
644 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */
645 sljit_s32 dst_r = TMP_REG2;
648 sljit_s32 sugg_src2_r = TMP_REG2;
737 SLJIT_ASSERT(src2_r == TMP_REG2);
739 FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, TMP_REG2, src2, src2w, src1, src1w));
744 FAIL_IF(getput_arg(compiler, flags | LOAD_DATA, TMP_REG2, src2, src2w, dst, dstw));
797 FAIL_IF(push_inst(compiler, OR | D(TMP_REG2) | S1(0) | S2(SLJIT_R0), DR(TMP_REG2)))
[all...] |
| sljitNativeARM_T2_32.c | 37 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
515 arg2 must be register, TMP_REG2, imm */
668 FAIL_IF(load_immediate(compiler, TMP_REG2, arg2));
669 arg2 = TMP_REG2;
750 SLJIT_ASSERT(reg_map[TMP_REG2] <= 7 && dst != TMP_REG2);
751 FAIL_IF(push_inst32(compiler, SMULL | RT4(dst) | RD4(TMP_REG2) | RN4(arg1) | RM4(arg2)));
752 /* cmp TMP_REG2, dst asr #31. */
753 return push_inst32(compiler, CMP_W | RN4(TMP_REG2) | 0x70e0 | RM4(dst));
[all...] |
| sljitNativeMIPS_common.c | 48 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
52 #define PIC_ADDR_REG TMP_REG2
567 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | TA(0) | D(TMP_REG2), DR(TMP_REG2)));
569 base = S(TMP_REG2);
903 arg2 goes to TMP_REG2, imm or src reg
905 result goes to TMP_REG2, so put result can use TMP_REG1 and TMP_REG3. */
906 sljit_s32 dst_r = TMP_REG2;
909 sljit_s32 sugg_src2_r = TMP_REG2;
1004 SLJIT_ASSERT(src2_r == TMP_REG2)
[all...] |
| sljitNativeMIPS_32.c | 228 FAIL_IF(push_inst(compiler, ADDIU | SA(0) | T(TMP_REG2) | IMM(src2), DR(TMP_REG2)));
229 src2 = TMP_REG2;
275 FAIL_IF(push_inst(compiler, ADDIU | SA(0) | T(TMP_REG2) | IMM(src2), DR(TMP_REG2)));
276 src2 = TMP_REG2;
|
| sljitNativeMIPS_64.c | 320 FAIL_IF(push_inst(compiler, ADDIU | SA(0) | T(TMP_REG2) | IMM(src2), DR(TMP_REG2)));
321 src2 = TMP_REG2;
367 FAIL_IF(push_inst(compiler, ADDIU | SA(0) | T(TMP_REG2) | IMM(src2), DR(TMP_REG2)));
368 src2 = TMP_REG2;
|
| sljitNativeARM_32.c | 40 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
[all...] |
| sljitNativeARM_64.c | 38 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
519 arg2 must be register, TMP_REG2, imm */
646 FAIL_IF(load_immediate(compiler, TMP_REG2, arg2));
647 arg2 = TMP_REG2;
[all...] |
| sljitNativeX86_common.c | 84 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
713 FAIL_IF(emit_load_imm64(compiler, TMP_REG2, srcw));
714 inst = emit_x86_instruction(compiler, 1, TMP_REG2, 0, dst, dstw);
[all...] |
| sljitNativeTILEGX_64.c | 47 #define TMP_REG2 (SLJIT_NUMBER_OF_REGISTERS + 3)
50 #define PIC_ADDR_REG TMP_REG2
[all...] |
