/external/vixl/src/aarch64/ |
operands-aarch64.cc | 336 (reg_.IsW() && ((extend_ == UXTW) || (extend_ == SXTW))))); 362 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); 401 VIXL_ASSERT((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 462 VIXL_ASSERT((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX));
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constants-aarch64.h | 287 UXTW = 2, [all...] |
simulator-aarch64.cc | 394 case UXTW: [all...] |
/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AddressingModes.h | 42 UXTW, 62 case AArch64_AM::UXTW: return "uxtw"; 129 case 2: return AArch64_AM::UXTW; 145 /// 010 ==> uxtw 156 case AArch64_AM::UXTW: return 2; break; 192 /// 010 ==> uxtw
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/prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
anames.go | 236 "UXTW",
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/prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
anames.go | 236 "UXTW",
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
addsub.s | 102 .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
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/external/v8/src/compiler/arm64/ |
code-generator-arm64.cc | 438 __ Ldr(result, MemOperand(buffer, offset, UXTW)); \ 450 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \ 462 __ asm_instr(result, MemOperand(buffer, offset, UXTW)); \ 474 __ Str(value, MemOperand(buffer, offset, UXTW)); \ 486 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \ 498 __ asm_instr(value, MemOperand(buffer, offset, UXTW)); \ [all...] |
/external/vixl/test/aarch64/ |
test-disasm-aarch64.cc | 428 COMPARE(adds(x9, x10, Operand(x11, UXTW, 3)), "adds x9, x10, w11, uxtw #3"); 440 COMPARE(add(wsp, wsp, Operand(w4, UXTW, 2)), "add wsp, wsp, w4, lsl #2"); 454 COMPARE(subs(x9, x10, Operand(x11, UXTW, 3)), "subs x9, x10, w11, uxtw #3"); 466 COMPARE(sub(wsp, wsp, Operand(w4, UXTW, 2)), "sub wsp, wsp, w4, lsl #2"); 590 COMPARE(uxtw(x18, x19), "ubfx x18, x19, #0, #32"); [all...] |
test-simulator-aarch64.cc | 229 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)); 351 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 355 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 486 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 490 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 494 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift)); 633 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 637 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift)); 770 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift)); 897 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift)) [all...] |
test-assembler-aarch64.cc | 329 __ Mvn(x14, Operand(w2, UXTW, 4)); 504 __ Mov(x27, Operand(w13, UXTW, 4)); 565 __ Mov(x29, Operand(x12, UXTW, 1)); 637 __ Orr(w8, w0, Operand(w1, UXTW, 2)); 731 __ Orn(w8, w0, Operand(w1, UXTW, 2)); 798 __ And(w8, w0, Operand(w1, UXTW, 2)); 936 __ Bic(w8, w0, Operand(w1, UXTW, 2)); 1060 __ Eor(w8, w0, Operand(w1, UXTW, 2)); 1127 __ Eon(w8, w0, Operand(w1, UXTW, 2)); [all...] |
/external/v8/src/arm64/ |
assembler-arm64-inl.h | 383 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); 466 DCHECK((extend == UXTW) || (extend == SXTW) || (extend == SXTX)); 519 DCHECK((extend_ == UXTW) || (extend_ == SXTW) || (extend_ == SXTX)); [all...] |
constants-arm64.h | 341 UXTW = 2, [all...] |
code-stubs-arm64.cc | [all...] |
simulator-arm64.cc | [all...] |
assembler-arm64.cc | [all...] |
macro-assembler-arm64.cc | [all...] |
/art/compiler/optimizing/ |
common_arm64.h | 333 case HDataProcWithShifterOp::kUXTW: return vixl::aarch64::UXTW;
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/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 361 UXTW,
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/external/v8/src/regexp/arm64/ |
regexp-macro-assembler-arm64.cc | 191 __ Add(x10, code_pointer(), Operand(w10, UXTW)); 581 __ Ldrb(w11, MemOperand(x11, w10, UXTW)); 662 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); 675 __ Ldrb(w10, MemOperand(x10, current_character(), UXTW)); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 670 Addr.setExtendType(AArch64_AM::UXTW); 694 Addr.setExtendType(AArch64_AM::UXTW); 754 Addr.setExtendType(AArch64_AM::UXTW); 791 Addr.setExtendType(AArch64_AM::UXTW); 813 Addr.setExtendType(AArch64_AM::UXTW); [all...] |
AArch64ISelDAGToDAG.cpp | 393 return AArch64_AM::UXTW; 411 return AArch64_AM::UXTW; 547 /// Instructions that accept extend modifiers like UXTW expect the register [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | 990 ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW || 1025 return (ET == AArch64_AM::UXTW || ET == AArch64_AM::SXTW) && [all...] |
/external/v8/src/crankshaft/arm64/ |
lithium-codegen-arm64.cc | [all...] |