| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| addsub.s | 29 // or implicitly UXTX, SXTX or LSL; otherwise it Wm.
31 .ifnc \extend, UXTX
102 .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
|
| illegal.s | 482 add x0, x1, #20, UXTX #12
|
| /external/vixl/src/aarch64/ |
| operands-aarch64.cc | 321 // Extend modes SXTX and UXTX require a 64-bit register.
322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
335 ((extend_ == UXTX) || (extend_ == SXTX) ||
362 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
|
| disasm-aarch64.cc | 165 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext"
168 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext";
[all...] |
| macro-assembler-aarch64.cc | 855 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
[all...] |
| constants-aarch64.h | 288 UXTX = 3,
[all...] |
| simulator-aarch64.cc | 415 case UXTX:
[all...] |
| assembler-aarch64.cc | [all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AddressingModes.h | 43 UXTX,
63 case AArch64_AM::UXTX: return "uxtx";
130 case 3: return AArch64_AM::UXTX;
146 /// 011 ==> uxtx
157 case AArch64_AM::UXTX: return 3; break;
193 /// 011 ==> uxtx
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 362 UXTX,
|
| /external/v8/src/arm64/ |
| disasm-arm64.cc | 144 const char *form = ((mode == UXTX) || (mode == SXTX)) ?
146 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ?
[all...] |
| assembler-arm64-inl.h | 351 // Extend modes SXTX and UXTX require a 64-bit register.
352 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
383 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
[all...] |
| constants-arm64.h | 342 UXTX = 3,
[all...] |
| assembler-arm64.cc | [all...] |
| simulator-arm64.cc | [all...] |
| macro-assembler-arm64.cc | 147 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
549 ((operand.extend() != UXTX) && (operand.extend() != SXTX)));
[all...] |
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 991 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
999 // UXTX and SXTX require a 64-bit source register (the ExtendLSL64 class).
1001 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX;
1007 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX ||
[all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | 638 __ Orr(x9, x0, Operand(x1, UXTX, 3));
732 __ Orn(x9, x0, Operand(x1, UXTX, 3));
799 __ And(x9, x0, Operand(x1, UXTX, 3));
937 __ Bic(x9, x0, Operand(x1, UXTX, 3));
1061 __ Eor(x9, x0, Operand(x1, UXTX, 3));
1128 __ Eon(x9, x0, Operand(x1, UXTX, 3));
[all...] |
| test-disasm-aarch64.cc | 429 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4");
441 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3");
455 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4");
467 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3");
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| AArch64ISelDAGToDAG.cpp | 596 assert(Ext != AArch64_AM::UXTX && Ext != AArch64_AM::SXTX);
[all...] |
