/external/llvm/lib/Target/Hexagon/ |
HexagonBitTracker.cpp | 241 uint16_t W0 = (Reg[0].Reg != 0) ? getRegBitWidth(Reg[0]) : 0; 253 return rr0(eIMM(im(1), W0), Outputs); 255 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::Zero), Outputs); 257 return rr0(RegisterCell(W0).fill(0, W0, BT::BitValue::One), Outputs); 263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); 275 uint16_t RW = W0; 284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); 285 W0 = 8; // XXX Pred siz [all...] |
HexagonRegisterInfo.cpp | 75 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
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/art/compiler/utils/mips64/ |
managed_register_mips64_test.cc | 111 Mips64ManagedRegister vreg = Mips64ManagedRegister::FromVectorRegister(W0); 118 EXPECT_EQ(W0, reg.AsOverlappingVectorRegister()); 156 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0); 163 EXPECT_EQ(W0, reg.AsVectorRegister()); 165 EXPECT_TRUE(reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); 208 EXPECT_FALSE(no_reg.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); 216 EXPECT_FALSE(reg_ZERO.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); 225 EXPECT_FALSE(reg_A1.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); 234 EXPECT_FALSE(reg_S2.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); 244 EXPECT_FALSE(reg_F0.Equals(Mips64ManagedRegister::FromVectorRegister(W0))); [all...] |
/external/boringssl/src/crypto/fipsmodule/sha/asm/ |
sha512-armv8.pl | 351 my ($W0,$W1)=("v16.4s","v17.4s"); 369 ld1.32 {$W0},[$Ktbl],#16 380 add.i32 $W0,$W0,@MSG[0] 383 sha256h $ABCD,$EFGH,$W0 384 sha256h2 $EFGH,$abcd,$W0 387 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG)); 391 add.i32 $W0,$W0,@MSG[0 [all...] |
sha256-armv4.pl | 599 my ($W0,$W1,$ABCD_SAVE,$EFGH_SAVE)=map("q$_",(12..15)); 624 vld1.32 {$W0},[$Ktbl]! 636 vadd.i32 $W0,$W0,@MSG[0] 639 sha256h $ABCD,$EFGH,$W0 640 sha256h2 $EFGH,$abcd,$W0 643 ($W0,$W1)=($W1,$W0); push(@MSG,shift(@MSG)); 647 vadd.i32 $W0,$W0,@MSG[0 [all...] |
sha1-armv8.pl | 246 my ($W0,$W1)=("v20.4s","v21.4s"); 270 add.i32 $W0,@Kxx[0],@MSG[0] 277 sha1c $ABCD,$E,$W0 // 0 278 add.i32 $W0,@Kxx[$j],@MSG[2] 292 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 301 sha1p $ABCD,$E0,$W0
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sha1-armv4-large.pl | 615 my ($W0,$W1,$ABCD_SAVE)=map("q$_",(12..14)); 648 vadd.i32 $W0,@Kxx[0],@MSG[0] 656 sha1c $ABCD,$E,$W0 657 vadd.i32 $W0,@Kxx[$j],@MSG[2] 671 ($E0,$E1)=($E1,$E0); ($W0,$W1)=($W1,$W0); 680 sha1p $ABCD,$E0,$W0
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/art/runtime/arch/arm64/ |
registers_arm64.cc | 32 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", 48 if (rhs >= W0 && rhs < kNumberOfWRegisters) {
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registers_arm64.h | 75 W0 = 0,
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/art/runtime/arch/mips/ |
registers_mips.cc | 49 if (rhs >= W0 && rhs < kNumberOfVectorRegisters) {
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registers_mips.h | 111 W0 = 0,
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/art/runtime/arch/mips64/ |
registers_mips64.cc | 50 if (rhs >= W0 && rhs < kNumberOfVectorRegisters) {
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registers_mips64.h | 112 W0 = 0,
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/external/libopus/src/ |
mlp_train.c | 117 double *W0, *W1; 130 W0 = net->weights[0]; 145 double sum = W0[i*(inDim+1)]; 147 sum += W0[i*(inDim+1)+j+1]*in[j]; 232 double *W0, *W1, *best_W0, *best_W1; 253 W0 = net->weights[0]; 269 memcpy(W0_old, W0, W0_size*sizeof(double)); 270 memcpy(W0_old2, W0, W0_size*sizeof(double)); 329 best_W0[i] = W0[i]; 347 W0[i] = best_W0[i] [all...] |
/device/linaro/bootloader/edk2/Nt32Pkg/Sec/ |
SecMain.inf | 75 MSFT:*_*_IA32_ASM_FLAGS == /nologo /W3 /WX /c /coff /Cx /Zd /W0 /Zi
83 MSFT:*_*_X64_ASM_FLAGS == /nologo /W3 /WX /c /Cx /Zd /W0 /Zi
89 INTEL:*_*_IA32_ASM_FLAGS == /nologo /W3 /WX /c /coff /Cx /Zd /W0 /Zi
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/libcore/luni/src/test/java/libcore/java/lang/ |
ClassCastExceptionTest.java | 81 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0, 86 A0, B0, C0, D0, E0, F0, G0, H0, I0, J0, K0, L0, M0, N0, O0, P0, Q0, R0, S0, T0, U0, V0, W0, X0, Y0, Z0,
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/art/compiler/jni/quick/arm64/ |
calling_convention_arm64.cc | 39 W0, W1, W2, W3, W4, W5, W6, W7 142 return Arm64ManagedRegister::FromWRegister(W0); 155 return Arm64ManagedRegister::FromWRegister(W0);
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/external/mesa3d/src/intel/isl/ |
isl.c | 731 uint32_t W0 = phys_level0_sa->w; 735 uint32_t W = isl_minify(W0, l); 780 uint32_t W0 = phys_level0_sa->w; 785 uint32_t level_w = isl_align_npot(isl_minify(W0, l), image_align_sa->w); 822 const uint32_t W0 = phys_level0_sa->w; 825 uint32_t W = isl_minify(W0, l); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64CallLowering.cpp | 42 unsigned ResReg = (Size == 32) ? AArch64::W0 : AArch64::X0;
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/external/llvm/test/MC/AArch64/ |
arm64-leaf-compact-unwind.s | 74 add w0, w0, #42 ; =#42 96 mov w0, wzr 102 add w0, w10, w0 149 ldr w0, [x8] 166 add w9, w9, w0 181 sub w0, w8, w1, lsl #1 203 ; kill: W0<def> W0<kill> X0<def [all...] |
/art/compiler/utils/arm64/ |
managed_register_arm64_test.cc | 34 Arm64ManagedRegister wreg = Arm64ManagedRegister::FromWRegister(W0); 106 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); 114 EXPECT_EQ(W0, reg.AsWRegister()); 273 EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromWRegister(W0))); 282 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromWRegister(W0))); 326 EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromWRegister(W0))); 336 EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromWRegister(W0))); 346 EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromWRegister(W0))); 366 EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromWRegister(W0))); 376 Arm64ManagedRegister reg_o = Arm64ManagedRegister::FromWRegister(W0); [all...] |
/external/libyuv/files/util/ |
ssim.cc | 72 } W0 = MAKE_WEIGHT(0), W1 = MAKE_WEIGHT(1), W2 = MAKE_WEIGHT(2), 250 const __m128i w0 = _mm_unpacklo_epi8(v0, zero); \ 252 const __m128i ww0 = _mm_mullo_epi16(w0, (WEIGHT).values_.m_); \ 258 xx = _mm_add_epi32(xx, _mm_madd_epi16(ww0, w0)); \ 270 LOAD_LINE_PAIR(0, W0); 276 LOAD_LINE_PAIR(6, W0);
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/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 32 case AArch64::X0: return AArch64::W0; 72 case AArch64::W0: return AArch64::X0;
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/external/mesa3d/src/mesa/program/ |
prog_noise.c | 501 float W0 = l - t; 506 float w0 = w - W0; local 510 * determine the magnitude ordering of x0, y0, z0 and w0. 520 int c4 = (x0 > w0) ? 4 : 0; 521 int c5 = (y0 > w0) ? 2 : 0; 522 int c6 = (z0 > w0) ? 1 : 0; 561 w1 = w0 - l1 + G4; 565 w2 = w0 - l2 + 2.0f * G4; 569 w3 = w0 - l3 + 3.0f * G4 [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCodeEmitter.cpp | 98 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15) 100 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
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