| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.cpp | 38 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
39 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
40 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
41 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
42 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
43 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 53 addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
54 addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
55 addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
56 addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 58 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
59 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
61 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
62 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
64 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
65 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
66 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
68 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
69 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
71 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass)
[all...] |
| R600ISelLowering.cpp | 36 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
37 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
38 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass);
39 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
40 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
41 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 107 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
109 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
111 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
112 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
113 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass);
394 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
395 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
396 addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 50 addRegisterClass(MVT::i32, BF::DRegisterClass);
51 addRegisterClass(MVT::i16, BF::D16RegisterClass);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 54 addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
55 addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
56 addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 693 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
694 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
695 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
63 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
247 addRegisterClass(Ty, RC);
296 addRegisterClass(Ty, RC);
[all...] |
| Mips16ISelLowering.cpp | 126 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 65 addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
67 addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelLowering.cpp | 227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
551 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
552 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
583 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
584 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
616 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
617 addRegisterClass(MVT::f32, X86::RFP32RegisterClass)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
106 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 82 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
141 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
402 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
524 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
525 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
526 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
527 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
610 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | 95 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
96 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
99 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
104 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass);
106 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 135 addRegisterClass(MVT::i8, &X86::GR8RegClass);
136 addRegisterClass(MVT::i16, &X86::GR16RegClass);
137 addRegisterClass(MVT::i32, &X86::GR32RegClass);
139 addRegisterClass(MVT::i64, &X86::GR64RegClass);
487 addRegisterClass(MVT::f32, &X86::FR32RegClass);
488 addRegisterClass(MVT::f64, &X86::FR64RegClass);
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
553 addRegisterClass(MVT::f32, &X86::RFP32RegClass)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 137 addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
138 addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
139 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
140 addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
141 addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
142 addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 65 addRegisterClass(MVT::i8, &MSP430::GR8RegClass);
66 addRegisterClass(MVT::i16, &MSP430::GR16RegClass);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 69 addRegisterClass(MVT::i8, MSP430::GR8RegisterClass);
70 addRegisterClass(MVT::i16, MSP430::GR16RegisterClass);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
274 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
350 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
351 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
352 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
353 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 59 addRegisterClass(MVT::i64, &BPF::GPRRegClass);
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetLowering.h | [all...] |
