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  /external/mesa3d/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_surface.h 31 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id, enum chip_class chip_class);
radv_amdgpu_winsys.h 41 struct amdgpu_gpu_info amdinfo; member in struct:radv_amdgpu_winsys
radv_amdgpu_winsys.c 138 r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
180 ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
181 ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
278 ws->addrlib = radv_amdgpu_addr_create(&ws->amdinfo, ws->family, ws->rev_id, ws->info.chip_class);
293 ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
294 ws->info.max_se = ws->amdinfo.num_shader_engines;
295 ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
299 ws->info.num_render_backends = ws->amdinfo.rb_pipes;
300 ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
301 ws->info.num_tile_pipes = radv_cik_get_num_tile_pipes(&ws->amdinfo);
    [all...]
radv_amdgpu_surface.c 114 ADDR_HANDLE radv_amdgpu_addr_create(struct amdgpu_gpu_info *amdinfo, int family, int rev_id,
126 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3;
127 regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
128 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2;
130 regValue.backendDisables = amdinfo->backend_disable[0];
131 regValue.pTileConfig = amdinfo->gb_tile_mode;
132 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode);
137 regValue.pMacroTileConfig = amdinfo->gb_macro_tile_mode;
138 regValue.noOfMacroEntries = ARRAY_SIZE(amdinfo->gb_macro_tile_mode);
  /external/mesa3d/src/gallium/winsys/amdgpu/drm/
amdgpu_winsys.c 123 r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
201 ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
202 ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
320 !(ws->amdinfo.ids_flags & AMDGPU_IDS_FLAGS_FUSION);
330 ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
331 ws->info.max_se = ws->amdinfo.num_shader_engines;
332 ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
339 ws->info.num_render_backends = ws->amdinfo.rb_pipes;
340 ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
341 ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
    [all...]
amdgpu_winsys.h 72 struct amdgpu_gpu_info amdinfo; member in struct:amdgpu_winsys
amdgpu_surface.c 110 regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
111 regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
112 regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
114 regValue.backendDisables = ws->amdinfo.backend_disable[0];
115 regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
116 regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
121 regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
122 regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);

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