| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.h | 38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
|
| LanaiInstrInfo.cpp | 89 bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
|
| AArch64LoadStoreOptimizer.cpp | [all...] |
| AArch64InstrInfo.cpp | 657 bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint(
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
|
| HexagonExpandCondsets.cpp | 824 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.h | 167 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
|
| SIInstrInfo.cpp | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/CodeGen/ |
| ScheduleDAGInstrs.cpp | 572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA))
[all...] |
| MachinePipeliner.cpp | [all...] |
