| /external/mesa3d/src/amd/addrlib/r800/ |
| siaddrlib.h | 132 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
164 UINT_32 baseAlign, UINT_32 pitchAlign,
191 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
|
| egbaddrlib.h | 169 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
177 UINT_32 baseAlign, UINT_32 pitchAlign,
287 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
|
| egbaddrlib.cpp | 233 &pOut->baseAlign,
276 pOut->baseAlign,
357 &pOut->baseAlign,
386 pOut->baseAlign,
449 &pOut->baseAlign,
508 &pOut->baseAlign,
[all...] |
| siaddrlib.cpp | 777 UINT_32 baseAlign ///< [in] base alignments
780 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
[all...] |
| /external/mesa3d/src/amd/addrlib/core/ |
| addrlib.cpp | [all...] |
| addrlib.h | 365 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const = 0;
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_surface.c | 192 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
265 surf->htile_alignment = AddrHtileOut->baseAlign;
508 surf->surf_alignment = AddrSurfInfoOut.baseAlign;
|
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_surface.c | 203 surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
467 surf->bo_alignment = AddrSurfInfoOut.baseAlign;
|
| /external/mesa3d/src/amd/addrlib/ |
| addrinterface.h | 531 UINT_32 baseAlign; ///< Base address alignment
[all...] |
