| /external/valgrind/none/tests/mips32/ |
| fpu_branches.stdout.exp | 1 --- BC1F --- if fs != ft then out = fs else out = fs + ft
2 bc1f, c.eq.s out=0.000000, fs=0.000000, ft=-4578.500000
3 bc1f, c.eq.d out=0.000000, fs=0.000000, ft=-45786.500000
4 bc1f, c.eq.s out=912.500000, fs=456.250000, ft=456.250000
5 bc1f, c.eq.d out=912.500000, fs=456.250000, ft=456.250000
6 bc1f, c.eq.s out=3.000000, fs=3.000000, ft=34.031250
7 bc1f, c.eq.d out=3.000000, fs=3.000000, ft=34.031250
8 bc1f, c.eq.s out=-1.000000, fs=-1.000000, ft=4578.750000
9 bc1f, c.eq.d out=-1.000000, fs=-1.000000, ft=45786.750000
10 bc1f, c.eq.s out=1384.500000, fs=1384.500000, ft=175.00000
[all...] |
| /external/valgrind/none/tests/mips64/ |
| fpu_branches.stdout.exp | 1 --- BC1F --- if fs == ft then out = ft else out = fs + ft
2 bc1f, c.eq.s out=-4578.500000, fs=0.000000, ft=-4578.500000
3 bc1f, c.eq.d out=-45786.500000, fs=0.000000, ft=-45786.500000
4 bc1f, c.eq.s out=912.500000, fs=456.250000, ft=456.250000
5 bc1f, c.eq.d out=912.500000, fs=456.250000, ft=456.250000
6 bc1f, c.eq.s out=34.031250, fs=3.000000, ft=34.031250
7 bc1f, c.eq.d out=34.031250, fs=3.000000, ft=34.031250
8 bc1f, c.eq.s out=4578.750000, fs=-1.000000, ft=4578.750000
9 bc1f, c.eq.d out=45786.750000, fs=-1.000000, ft=45786.750000
10 bc1f, c.eq.s out=175.000000, fs=1384.500000, ft=175.00000
[all...] |
| /external/llvm/test/MC/Mips/ |
| micromips-bad-branches.s | 94 # CHECK: bc1f -65535
96 # CHECK: bc1f -65537
98 # CHECK: bc1f 65535
100 # CHECK: bc1f 65536
103 # CHECK: bc1f $fcc0, -65535
105 # CHECK: bc1f $fcc0, -65537
107 # CHECK: bc1f $fcc0, 65535
109 # CHECK: bc1f $fcc0, 65536
204 bc1f -65535
205 bc1f -6553
[all...] |
| mips-bad-branches.s | 174 # CHECK: bc1f -131069
176 # CHECK: bc1f -131070
178 # CHECK: bc1f -131071
180 # CHECK: bc1f -131073
182 # CHECK: bc1f 131069
184 # CHECK: bc1f 131070
186 # CHECK: bc1f 131071
188 # CHECK: bc1f 131072
191 # CHECK: bc1f $fcc0, -131069
193 # CHECK: bc1f $fcc0, -13107
[all...] |
| mips-jump-delay-slots.s | 10 # CHECK: bc1f 1332
12 bc1f 1332
|
| mips-jump-instructions.s | 13 # CHECK32: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45]
38 # CHECK64: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45]
65 bc1f 1332
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| movem-to-reg.d | 86 [ ]+17a:[ ]+42a5 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2\+\$?r10\.b\],\$?r1
103 [ ]+1be:[ ]+0021 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2\+0\],\$?r1
104 [ ]+1c2:[ ]+0121 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2\+1\],\$?r1
105 [ ]+1c6:[ ]+7f21 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2\+127\],\$?r1
106 [ ]+1ca:[ ]+5f2d 8000 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2\+128\],\$?r1
107 [ ]+1d0:[ ]+ff21 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2-1\],\$?r1
108 [ ]+1d4:[ ]+ff21 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2-1\],\$?r1
109 [ ]+1d8:[ ]+8121 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2-127\],\$?r1
110 [ ]+1dc:[ ]+8021 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2-128\],\$?r1
111 [ ]+1e0:[ ]+8121 bc1f[ ]+movem[ ]+\[\$?r12=\$?r2-127\],\$?r
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips@mips4-branch-likely.d | 11 [0-9a-f]+ <[^>]*> 4384 fffe bc1f \$fcc1,0+0000 <text_label>
|
| relax.s | 17 bc1f bar
45 bc1f foo
|
| mips4-fp.s | 4 bc1f text_label
5 bc1f $fcc1,text_label
|
| mips4-fp.d | 9 [0-9a-f]+ <[^>]*> bc1f 0+0000 <text_label>
11 [0-9a-f]+ <[^>]*> bc1f \$fcc1,0+0000 <text_label>
|
| set-arch.s | 40 bc1f text_label
41 bc1f $fcc1,text_label
|
| micromips@mips4-fp.d | 11 [0-9a-f]+ <[^>]*> 4380 fffe bc1f 0+0000 <text_label>
14 [0-9a-f]+ <[^>]*> 4384 fffe bc1f \$fcc1,0+0006 <text_label\+0x6>
|
| mips4-fp.l | 2 .*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
3 .*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
|
| micromips-branch-relax.s | 95 bc1f test3
|
| /art/runtime/interpreter/mterp/mips/ |
| op_double_to_long.S | 24 bc1f fcc0, .L${opcode}_get_opcode
|
| op_float_to_long.S | 23 bc1f fcc0, .L${opcode}_get_opcode
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 8 bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
20 bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
21 bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
|
