| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| branch-misc-3.d | 17 .* bc1t .*
26 .* bc1t .*
32 .* bc1t .*
38 .* bc1t .*
43 .* bc1t .*
49 .* bc1t .*
54 .* bc1t .*
57 .* bc1t .*
|
| micromips@mips4-branch-likely.d | 14 [0-9a-f]+ <[^>]*> 43a8 fffe bc1t \$fcc2,0+0006 <text_label\+0x6>
|
| relax.s | 18 bc1t bar
46 bc1t foo
|
| relax-swap1.s | 71 bc1t foo
73 bc1t bar
|
| micromips@mips32-cp2.s | 31 # Cop2 branches with cond code number, like bc1t/f.
|
| mips32-cp2.s | 34 # Cop2 branches with cond code number, like bc1t/f
|
| mips4-fp.s | 6 bc1t $fcc1,text_label
|
| mips4-fp.d | 13 [0-9a-f]+ <[^>]*> bc1t \$fcc1,0+0000 <text_label>
|
| mips4-fp.l | 4 .*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
|
| micromips-branch-relax.s | 97 bc1t test3
|
| set-arch.s | 43 bc1t $fcc1,text_label
|
| micromips@mips4-fp.d | 17 [0-9a-f]+ <[^>]*> 43a4 fffe bc1t \$fcc1,0+000c <text_label\+0xc>
|
| /external/llvm/test/MC/Mips/ |
| micromips-bad-branches.s | 112 # CHECK: bc1t -65535
114 # CHECK: bc1t -65537
116 # CHECK: bc1t 65535
118 # CHECK: bc1t 65536
121 # CHECK: bc1t $fcc0, -65535
123 # CHECK: bc1t $fcc0, -65537
125 # CHECK: bc1t $fcc0, 65535
127 # CHECK: bc1t $fcc0, 65536
218 bc1t -65535
219 bc1t -6553
[all...] |
| mips-bad-branches.s | 208 # CHECK: bc1t -131069
210 # CHECK: bc1t -131070
212 # CHECK: bc1t -131071
214 # CHECK: bc1t -131073
216 # CHECK: bc1t 131069
218 # CHECK: bc1t 131070
220 # CHECK: bc1t 131071
222 # CHECK: bc1t 131072
225 # CHECK: bc1t $fcc0, -131069
227 # CHECK: bc1t $fcc0, -13107
[all...] |
| mips-jump-delay-slots.s | 13 # CHECK: bc1t 1332
15 bc1t 1332
|
| mips-jump-instructions.s | 15 # CHECK32: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
40 # CHECK64: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
67 bc1t 1332
|
| /art/runtime/interpreter/mterp/mips/ |
| op_cmpl_float.S | 33 bc1t fcc0, 1f # done if vBB == vCC (ordered)
37 bc1t fcc0, 1f # done if vBB < vCC (ordered)
42 bc1t fcc0, 1f # done if vBB > vCC (ordered)
|
| op_double_to_long.S | 31 bc1t fcc0, .L${opcode}_get_opcode
37 bc1t fcc0, .L${opcode}_get_opcode
|
| op_float_to_long.S | 29 bc1t fcc0, .L${opcode}_get_opcode
35 bc1t fcc0, .L${opcode}_get_opcode
|
| op_float_to_int.S | 22 bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation
|
| op_cmpl_double.S | 35 bc1t fcc0, 1f # done if vBB == vCC (ordered)
39 bc1t fcc0, 1f # done if vBB < vCC (ordered)
44 bc1t fcc0, 1f # done if vBB > vCC (ordered)
|
| op_double_to_int.S | 23 bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation
|
| /external/llvm/test/MC/Mips/mips1/ |
| valid.s | 21 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
22 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips2/ |
| valid.s | 23 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
24 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
