/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
bic.s | 0 # bic test 3 bic r0,r1,r2 4 bic r26,fp,sp 5 bic ilink1,ilink2,blink 6 bic r56,r59,lp_count 8 bic r0,r1,0 9 bic r0,0,r2 10 bic 0,r1,r2 11 bic r0,r1,-1 12 bic r0,-1,r [all...] |
bic.d | 9 0: 00 84 00 70 70008400 bic r0,r1,r2 10 4: 00 b8 4d 73 734db800 bic gp,fp,sp 11 8: 00 3e af 73 73af3e00 bic ilink1,ilink2,blink 12 c: 00 f8 1d 77 771df800 bic r56,r59,lp_count 13 10: 00 fe 00 70 7000fe00 bic r0,r1,0 14 14: 00 84 1f 70 701f8400 bic r0,0,r2 15 18: 00 84 e0 77 77e08400 bic 0,r1,r2 16 1c: ff ff 00 70 7000ffff bic r0,r1,-1 17 20: ff 85 1f 70 701f85ff bic r0,-1,r2 18 24: 00 84 e0 77 77e08400 bic 0,r1,r [all...] |
/external/compiler-rt/lib/builtins/arm/ |
sync_fetch_and_nand_8.S | 19 bic rD_LO, rN_LO, rM_LO ; \ 20 bic rD_HI, rN_HI, rM_HI
|
sync_fetch_and_nand_4.S | 17 #define nand_4(rD, rN, rM) bic rD, rN, rM
|
bswapdi2.S | 33 bic r2, r2, #0xff0000 38 bic r0, r0, #0xff0000
|
bswapsi2.S | 32 bic r1, r1, #0xff0000
|
/external/llvm/test/MC/AArch64/ |
neon-mov.s | 71 bic v0.2s, #1 72 bic v1.2s, #0 73 bic v0.2s, #1, lsl #8 74 bic v0.2s, #1, lsl #16 75 bic v0.2s, #1, lsl #24 76 bic v0.4s, #1 77 bic v0.4s, #1, lsl #8 78 bic v0.4s, #1, lsl #16 79 bic v0.4s, #1, lsl #24 80 bic v15.4h, # [all...] |
alias-logicalimm.s | 6 bic x0, x1, #2 11 bic w0, w1, #2
|
neon-bitwise-instructions.s | 47 bic v0.8b, v1.8b, v2.8b 48 bic v0.16b, v1.16b, v2.16b 58 // CHECK: bic v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x0e] 59 // CHECK: bic v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x4e]
|
/device/linaro/bootloader/arm-trusted-firmware/lib/cpus/aarch64/ |
aem_generic.S | 41 bic x1, x1, #SCTLR_C_BIT 60 bic x1, x1, #SCTLR_C_BIT
|
cortex_a53.S | 43 bic x1, x1, #SCTLR_C_BIT 54 bic x0, x0, #CPUECTLR_SMP_BIT
|
/device/linaro/bootloader/arm-trusted-firmware/bl1/aarch64/ |
bl1_entrypoint.S | 51 bic x0, x0, #SCTLR_EE_BIT 106 bic w0, w0, #TCPAC_BIT 107 bic w0, w0, #TTA_BIT 108 bic w0, w0, #TFP_BIT
|
/device/linaro/bootloader/arm-trusted-firmware/bl31/aarch64/ |
bl31_entrypoint.S | 61 bic x0, x0, #SCTLR_EE_BIT 134 bic w1, w1, #TCPAC_BIT 135 bic w1, w1, #TTA_BIT 136 bic w1, w1, #TFP_BIT
|
/cts/tests/inputmethod/src/android/view/inputmethod/cts/ |
InputBindingTest.java | 41 BaseInputConnection bic = new BaseInputConnection(view, false); local 45 InputBinding inputBinding = new InputBinding(bic, binder, uid, pid); 46 new InputBinding(bic, inputBinding); 47 assertSame(bic, inputBinding.getConnection());
|
/art/runtime/arch/arm64/ |
memcmp16_arm64.S | 81 bic data1, data1, mask 82 bic data2, data2, mask 91 // Mask off 0xF to have shift amount. Why does ARM64 not have BIC with immediate?!?! 109 bic src1, src1, #7 110 bic src2, src2, #7
|
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
thumb2_invert.s | 12 bic r8, r2, #0x7fffffff
|
/bionic/libc/arch-arm64/generic/bionic/ |
strlen.S | 116 bic has_nul2, tmp3, tmp4 134 bic src, srcin, 15 156 bic has_nul2, tmp3, tmp4 171 bic has_nul1, tmp1, tmp2 190 bic has_nul2, tmp3, tmp4 199 bic has_nul2, tmp3, tmp4 208 bic src, srcin, 15
|
memcmp.S | 90 bic data1, data1, mask 91 bic data2, data2, mask 118 bic src1, src1, #7 119 bic src2, src2, #7
|
strcmp.S | 77 bic has_nul, tmp1, tmp2 /* Non-zero if NUL terminator. */ 115 bic has_nul, tmp1, tmp2 136 bic src1, src1, #7 137 bic src2, src2, #7
|
/bionic/libc/arch-arm/cortex-a15/bionic/ |
string_copy.S | 180 bic ip, ip, r2 185 bic ip, ip, r3 290 bic ip, ip, r2 338 bic ip, ip, r2 367 bic ip, ip, r2 379 bic ip, ip, r3 403 bic ip, ip, r2 411 bic ip, ip, r3 437 bic ip, ip, r3 477 bic ip, ip, r [all...] |
strlen.S | 94 bic ip, ip, r3 105 bic ip, ip, r2 110 bic ip, ip, r3
|
/bionic/libc/arch-arm/cortex-a9/bionic/ |
strlen.S | 77 bic ip, ip, r2 82 bic ip, ip, r3 158 bic ip, ip, r2
|
/device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ |
ModuleEntryPoint.S | 28 bic r0, r0, #0x00000002 // disable L2 cache
33 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
34 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
|
/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Scripts/uefi-aarch64-bootstrap/ |
boot.S | 106 bic x0, x0, #(1 << 3) // Disable virtual FIQ
107 bic x0, x0, #(1 << 4) // Disable virtual IRQ
108 bic x0, x0, #(1 << 5) // Disable virtual SError and Abort
|
/device/linaro/bootloader/edk2/BeagleBoardPkg/Sec/Arm/ |
ModuleEntryPoint.S | 28 bic r0, r0, #0x00000002 // disable L2 cache
33 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
34 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */
|